Von: David Laight [David.Laight@ACULAB.COM]
Gesendet: Mittwoch, 25. Februar 2015 13:01
An: Markus Stockhausen; linux-crypto@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Betreff: RE: [PATCH v1 1/3] SHA1 for PPC/SPE - assembler

From: Markus Stockhausen

quoted

[PATCH v1 1/3] SHA1 for PPC/SPE - assembler

This is the assembler code for SHA1 implementation with
the SIMD SPE instruction set. With the enhanced instruction
set we can operate on 2 32 bit words in parallel. That helps
reducing the time to calculate W16-W79. For increasing
performance even more the assembler function can compute
hashes for more than one 64 byte input block.

The state of the used SPE registers is preserved via the
stack so we can run from interrupt context

Does the ppc use the same kind of delayed state save for the SPE
resisters that x86 uses (at least on the BSDs) for its FP (etc) regs.

That would mean that the registers might contain values for
a different process, and that the cpu could receive an IPI
requesting they be written to the processes normal save area
so that they can be reloaded onto a different cpu.

Indeed SPE registers are lazy switched. enable_kernel_spe()
will take care of that. Additionally I had some discussions about 
interrupt context and its limitations. So

1) I implemented register saving in all patches (see AES & SHA256). 
This is because I know which registers I will overwrite. One should 
remember that SPE registers are shared with normal registers. So 
no big impact to save 32 bit or 64 bit of the non-volatile PPC 
registers.

2) And used disabling of preemption. But in contrast to other 
crypto algorithm implementations only for reasonable time intervals 

Markus