[PATCH v3 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW

On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW

Signed-off-by: Christophe Leroy <redacted>

---
v2 is a complete rework compared to v1
v3: fixing pte_update() and comments

 arch/powerpc/include/asm/pgtable-ppc32.h | 5 +++--
 arch/powerpc/include/asm/pte-8xx.h       | 9 ++++-----
 arch/powerpc/kernel/head_8xx.S           | 3 ---
 3 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index caf094a..b4e0c3b 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h

@@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p,
 	andc	%1,%0,%5\n\
 	or	%1,%1,%6\n\
 	/* 0x200 == Extended encoding, bit 22 */ \
-	/* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
+	/* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \
 	rlwimi	%1,%1,32-2,0x200\n /* get _PAGE_USER */ \
-	rlwinm	%3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+	rlwinm	%3,%1,32-1,0x200\n /* get _PAGE_RO */ \
+	xori	%3,%3,0x200\n \
 	or	%1,%3,%1\n\
 	xori	%1,%1,0x200\n"
 "	stwcx.	%1,0,%4\n\

diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index daa4616..eb6edb4 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h

@@ -46,9 +46,9 @@
  * require a TLB exception handler change.  It is assumed unused bits
  * are always zero.
  */
-#define _PAGE_RW	0x0400	/* lsb PP bits, inverted in HW */
+#define _PAGE_RO	0x0400	/* lsb PP bits */
 #define _PAGE_USER	0x0800	/* msb PP bits */
-/* set when neither _PAGE_USER nor _PAGE_RW are set */
+/* set when _PAGE_USER is unset and _PAGE_RO is set */
 #define _PAGE_KNLRO	0x0200
 
 #define _PMD_PRESENT	0x0001

@@ -62,9 +62,8 @@
 #define PTE_ATOMIC_UPDATES	1
 
 /* We need to add _PAGE_SHARED to kernel pages */
-#define _PAGE_KERNEL_RO	(_PAGE_SHARED | _PAGE_KNLRO)
-#define _PAGE_KERNEL_ROX	(_PAGE_EXEC | _PAGE_KNLRO)
-#define _PAGE_KERNEL_RW	(_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
+#define _PAGE_KERNEL_RO	(_PAGE_SHARED | _PAGE_RO | _PAGE_KNLRO)
+#define _PAGE_KERNEL_ROX	(_PAGE_EXEC | _PAGE_RO | _PAGE_KNLRO)
 
 #endif /* __KERNEL__ */
 #endif /*  _ASM_POWERPC_PTE_8xx_H */

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 3d4b8ee..807b0db 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S

@@ -441,9 +441,6 @@ DataStoreTLBMiss:
 	and	r11, r11, r10
 	rlwimi	r10, r11, 0, _PAGE_PRESENT
 #endif
-	/* invert RW */
-	xori	r10, r10, _PAGE_RW
-
 	/* The Linux PTE won't go exactly into the MMU TLB.
 	 * Software indicator bits 22 and 28 must be clear.
 	 * Software indicator bits 24, 25, 26, and 27 must be

-- 
2.1.0

On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:

On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_=

RW

=20
Signed-off-by: Christophe Leroy <redacted>

Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB patches
but got so little time :(

This is very cool (not sure if there will be a performance gain)  but ..

ude/asm/pgtable-ppc32.h

*/ \

+       /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is se=

t */ \

        rlwimi  %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
-       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RO */ \
+       xori    %3,%3,0x200\n \
        or      %1,%3,%1\n\
        xori    %1,%1,0x200\n"
 "      stwcx.  %1,0,%4\n\

... here I expected to loose the existing xori insn instead of adding one?

 Jocke=

Le 05/01/2015 19:12, Joakim Tjernlund a écrit :

On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:

quoted

On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW

Signed-off-by: Christophe Leroy <redacted>

Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB patches
but got so little time :(

This is very cool (not sure if there will be a performance gain)  but ..

I think every saved cycle is worth it.
Before I did any modification:
* ITLBMiss was 28 instructions.
* DTLBMiss was 32 instructions.
Now, (No MODULES, no CPU6, no CPU15):
* ITLBMiss is 15 instructions
* DTLBMiss is 24 instructions

quoted

diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index caf094a..b4e0c3b 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h

@@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p,
         andc    %1,%0,%5\n\
         or      %1,%1,%6\n\
         /* 0x200 == Extended encoding, bit 22 */ \
-       /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
+       /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \
         rlwimi  %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
-       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RO */ \
+       xori    %3,%3,0x200\n \
         or      %1,%3,%1\n\
         xori    %1,%1,0x200\n"
  "      stwcx.  %1,0,%4\n\

... here I expected to loose the existing xori insn instead of adding one?

Well, I could have xored the PAGE_USER bit instead, but in that case, it 
is not anymore an 'or' but an 'and' that has to be performed between the 
bits, and then all other bits must be set to 1, or the result of the 
'and' shall be inserted using 'rlwimi'. So it would be more 
modifications than just adding an xori, and not less instructions.

Christophe

On Tue, 2015-01-06 at 08:03 +0100, leroy christophe wrote:

Le 05/01/2015 19:12, Joakim Tjernlund a =E9crit :

quoted

On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:

quoted

On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only p=

ages

quoted

quoted

and is set to 0 for RW pages. So we should use _PAGE_RO instead of _P=

AGE_RW

quoted

quoted

=20
Signed-off-by: Christophe Leroy <redacted>

Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB pat=

ches

quoted

but got so little time :(
=20
This is very cool (not sure if there will be a performance gain)  but .=

.

I think every saved cycle is worth it.
Before I did any modification:
* ITLBMiss was 28 instructions.
* DTLBMiss was 32 instructions.
Now, (No MODULES, no CPU6, no CPU15):
* ITLBMiss is 15 instructions
* DTLBMiss is 24 instructions

I only meant this patch, sorry for not being explicit about that.

quoted

quoted

=20
=20

diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/=

include/asm/pgtable-ppc32.h

quoted

quoted

index caf094a..b4e0c3b 100644

--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h

@@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p,
         andc    %1,%0,%5\n\
         or      %1,%1,%6\n\
         /* 0x200 =3D=3D Extended encoding, bit 22 */ \
-       /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are =

set */ \

quoted

quoted

+       /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO i=

s set */ \

quoted

quoted

         rlwimi  %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
-       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RO */ \
+       xori    %3,%3,0x200\n \
         or      %1,%3,%1\n\
         xori    %1,%1,0x200\n"
  "      stwcx.  %1,0,%4\n\

... here I expected to loose the existing xori insn instead of adding o=

ne?

quoted

=20
=20

Well, I could have xored the PAGE_USER bit instead, but in that case, it
is not anymore an 'or' but an 'and' that has to be performed between the
bits, and then all other bits must be set to 1, or the result of the 'and=

' shall be inserted using 'rlwimi'. So it would be more modifications than =
just adding an xori, and not less instructions.

=20

I see, thanks

 Jocke=

On Tue, 2015-01-06 at 08:03 +0100, leroy christophe wrote:

Le 05/01/2015 19:12, Joakim Tjernlund a écrit :

quoted

On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:

quoted

On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW

Signed-off-by: Christophe Leroy <redacted>

Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB patches
but got so little time :(

This is very cool (not sure if there will be a performance gain)  but ..

I think every saved cycle is worth it.
Before I did any modification:
* ITLBMiss was 28 instructions.
* DTLBMiss was 32 instructions.
Now, (No MODULES, no CPU6, no CPU15):
* ITLBMiss is 15 instructions
* DTLBMiss is 24 instructions

quoted

quoted

diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index caf094a..b4e0c3b 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h

@@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p,
         andc    %1,%0,%5\n\
         or      %1,%1,%6\n\
         /* 0x200 == Extended encoding, bit 22 */ \
-       /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
+       /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \
         rlwimi  %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
-       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RO */ \
+       xori    %3,%3,0x200\n \
         or      %1,%3,%1\n\
         xori    %1,%1,0x200\n"
  "      stwcx.  %1,0,%4\n\

... here I expected to loose the existing xori insn instead of adding one?

Well, I could have xored the PAGE_USER bit instead, but in that case, it 
is not anymore an 'or' but an 'and' that has to be performed between the 
bits, and then all other bits must be set to 1, or the result of the 
'and' shall be inserted using 'rlwimi'. So it would be more 
modifications than just adding an xori, and not less instructions.

How about "andc %3,%3,%1; rlwimi %1,%3,0,0x200" instead of the "xori,
or, xori" sequence?

-Scott