[PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

STALE4364d REVIEWED: 1 (0M)

Revision v2 of 4 in this series; 1 review trailer.

2 messages, 2 authors, 2014-08-29 · open the first message on its own page

[PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

From: Christophe Leroy <hidden>
Date: 2014-08-29 09:13:28

This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885

The two differences with first version of the patch are:
1) I removed the patch number 10, which was implementing a 16 bit alignment of the
PGDIR. It is not worth potentially wasting up to 64k of memory just for removing one
instruction (ori).
2) I managed to preserve r11 while calculating the level 2 address, therefore
no more need to save r11 into CR.

Signed-off-by: Christophe Leroy <redacted>
Tested-by: Christophe Leroy <redacted>

 arch/powerpc/Kconfig                     |    2 +-
 arch/powerpc/include/asm/mmu-8xx.h       |    2 +
 arch/powerpc/include/asm/pgtable-ppc32.h |   21 ++
 arch/powerpc/include/asm/pte-8xx.h       |    7 +-
 arch/powerpc/include/asm/reg.h           |    3 +-
 arch/powerpc/kernel/head_8xx.S           |  342 +++++++++++-------------
 6 files changed, 187 insertions(+), 190 deletions(-)

Re: [PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

From: Joakim Tjernlund <hidden>
Date: 2014-08-29 15:22:03

Christophe Leroy [off-list ref] wrote on 2014/08/29 11:13:24:
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped 
with MPC885
The two differences with first version of the patch are:
1) I removed the patch number 10, which was implementing a 16 bit 
alignment of the
PGDIR. It is not worth potentially wasting up to 64k of memory just for 
removing one
instruction (ori).
2) I managed to preserve r11 while calculating the level 2 address, 
therefore
no more need to save r11 into CR.

Signed-off-by: Christophe Leroy <redacted>
Tested-by: Christophe Leroy <redacted>
This looks good but I need to look harder, some minor critique 
though(already sent)
 
As you are optimizing I think the impl.of powerpc/8xx: Invalidate non 
present TLBs 
in 2.4 is better than 3.x, compare:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/powerpc/mm/fault.c?id=5efab4a02c89c252fb4cce097aafde5f8208dbfe
with
https://git.kernel.org/cgit/linux/kernel/git/wtarreau/linux-2.4.git/commit/?id=da5c5609e86fb12061f2c05a6ddd80ffc46592b2


This will free the TLB before you jump to xxx_page_fault which might need 
a TLB before invalidation
and it isolates this 8xx quirk in 8xx specific code.

 Jocke
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