# Detecting LD/ST instruction

- From: Sukadev Bhattiprolu \<hidden\>
- Date: 2013-08-22 22:55:36 
- List: linuxppc-dev
- Page: https://ratatoskr.run/linuxppc-dev/2013/08/9476012
- Thread: https://ratatoskr.run/linuxppc-dev/2013/08/9476012/t.md

```text

I am working on implementing the 'perf mem' command for Power
systems. This would for instance, let us know where in the memory
hierarchy (L1, L2, Local RAM etc) the data for a load/store
instruction was found (hit).

On Power7, if the mcmcra[DCACHE_MISS] is clear _and_ the
instruction is a load/store, then it implies a L1-hit.

Unlike on Power8, the Power7 event vector has no indication
if the instruction was load/store.

In the context of a PMU interrupt, is there any way to determine
if an instruction is a load/store ?

Sukadev
```