On Mon, Aug 19, 2013 at 01:37:17PM +1000, Benjamin Herrenschmidt wrote:

On Mon, 2013-08-19 at 13:36 +1000, Benjamin Herrenschmidt wrote:

quoted

The semantic of this function is to make data executable. Even if the
implementation has a snooping icache, it *still* needs to make sure
prefetched code is tossed out of the pipeline which is what isync
should provide.

The architecture actually specifies that.

In fact, on P5 and later, I think we are supposed to do a single dummy
icbi followed by sync and isync.

Do you mean something like this? But why?

diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index d74fefb..8fcdec7 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S

@@ -69,6 +69,8 @@ PPC64_CACHES:
 
 _KPROBE(flush_icache_range)
 BEGIN_FTR_SECTION
+	icbi	0,r3
+	sync
 	isync
 	blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)

@@ -209,6 +211,8 @@ _GLOBAL(flush_inval_dcache_range)
  */
 _GLOBAL(__flush_dcache_icache)
 BEGIN_FTR_SECTION
+	icbi	0,r3
+	sync
 	isync
 	blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)

Thanks,
Kevin

Cheers,
Ben.

quoted

Cheers,
Ben.

quoted

quoted

 	blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	rlwinm	r3,r3,0,0,31-PAGE_SHIFT		/* Get page base address
*/

@@ -474,6 +475,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
  */
 _GLOBAL(__flush_dcache_icache_phys)
 BEGIN_FTR_SECTION
+	isync
 	blr					/* for 601, do nothing */
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 	mfmsr	r10

diff --git a/arch/powerpc/kernel/misc_64.S

b/arch/powerpc/kernel/misc_64.S
index 992a78e..d74fefb 100644

--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S

@@ -69,6 +69,7 @@ PPC64_CACHES:

 _KPROBE(flush_icache_range)
 BEGIN_FTR_SECTION
+	isync
 	blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 /*
--

1.8.3.1

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