[PATCH 1/1] Add a new platform tree for ib8315.
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From: Sergey Gerasimov <hidden>
Date: 2013-05-31 12:28:31
Subsystem:
linux for powerpc (32-bit and 64-bit), linux for powerpc embedded ppc8xx and ppc83xx, the rest · Maintainers:
Madhavan Srinivasan, Christophe Leroy, Linus Torvalds
Signed-off-by: Sergey Gerasimov <redacted> --- arch/powerpc/boot/dts/ib8315.dts | 490 +++++++++++++++++++++++++++++ arch/powerpc/configs/83xx/ib8315_defconfig | 102 ++++++ arch/powerpc/platforms/83xx/Kconfig | 7 + arch/powerpc/platforms/83xx/Makefile | 1 + arch/powerpc/platforms/83xx/tqm8315.c | 137 ++++++++ 5 files changed, 737 insertions(+) create mode 100644 arch/powerpc/boot/dts/ib8315.dts create mode 100644 arch/powerpc/configs/83xx/ib8315_defconfig create mode 100644 arch/powerpc/platforms/83xx/tqm8315.c
diff --git a/arch/powerpc/boot/dts/ib8315.dts b/arch/powerpc/boot/dts/ib8315.dts
new file mode 100644
index 0000000..963caf2
--- /dev/null
+++ b/arch/powerpc/boot/dts/ib8315.dts@@ -0,0 +1,490 @@ +/* + * IB8315 Device Tree Source based on: + * TQM8315 Device Tree Source + * + * Copyright 2009 TQ Components + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + compatible = "fsl,tqm8315"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8315@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0>; // from bootloader + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + + /* + * CS0 and CS1 are swapped when booting from nand, but the + * addresses are the same. + */ + ranges = <0x0 0x0 0x80000000 0x04000000 + 0x1 0x0 0xe0600000 0x00008000>; + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + /* + * The Intel PC48F4400P0TB00 chip has two non-identical + * dies. We need to define two seperate regions, that + * are scanned by physmap_of independently. Else, the + * MTD driver assumes two identical chips. + */ + reg = <0x0 0x00000000 0x02000000 + 0x0 0x02000000 0x02000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x80000>; // 512 KiB + read-only; + }; + + partition@1 { + label = "env1"; + reg = <0x80000 0x20000>; // 128 KiB + read-only; + }; + + partition@2 { + label = "env2"; + reg = <0xA0000 0x40000>; // 384 KiB + read-only; + }; + + partition@3 { + label ="dtb"; + reg = <0x100000 0x100000>; // 1 MiB + }; + + partition@4 { + label ="kernel"; + reg = <0x200000 0x300000>; // 3 MiB + }; + + partition@5 { + label ="root"; + reg = <0x500000 0x2800000>; // 40 MiB + }; + + /* + * The remaining 19 MiB, e.g. for a file system. + * Requires MTD concatenation support + */ + partition@6 { + label ="user"; + reg = <0x2D00000 0x1300000>; + }; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8315-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <0x1 0x0 0x8000>; + + partition@0 { + label = "filesystem"; + reg = <0x0 0x20000000>; + /*read-only;*/ + }; + }; + }; + + immr@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8315-immr", "simple-bus"; + ranges = <0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; // from bootloader + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <400000>; // SCL + dfsrr; + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + /* Enable this to support sensors on STK85xxNG */ + /*sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + sensor@4A { + compatible = "national,lm75"; + reg = <0x4A>; + }; + sensor@4B { + compatible = "national,lm75"; + reg = <0x4B>; + };*/ + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8315-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + cell-index = <0>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + cell-index = <3>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + dr_mode = "host"; + phy_type = "utmi"; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + // from bootloader + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = <&tbi0>; + phy-handle = < &phy0 >; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&ipic>; + interrupts = <20 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + + phy1: ethernet-phy@1 { + interrupt-parent = <&ipic>; + interrupts = <19 0x8>; + reg = <0x1>; + device_type = "ethernet-phy"; + }; + + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + // from bootloader + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 0x8 36 0x8 37 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = <&tbi1>; + phy-handle = < &phy1 >; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; // from bootloader + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; // from bootloader + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + crypto@30000 { + compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0", + "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x97c>; + fsl,descriptor-types-mask = <0x3ab0abf>; + }; + + sata@18000 { + compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + cell-index = <1>; + interrupts = <44 0x8>; + interrupt-parent = <&ipic>; + }; + + sata@19000 { + compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; + reg = <0x19000 0x1000>; + cell-index = <2>; + interrupts = <45 0x8>; + interrupt-parent = <&ipic>; + }; + + /* IPIC + * interrupts cell = <intr #, sense> + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: interrupt-controller@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + }; + + pci0: pci@e0008500 { + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + /* The values are calculated the following: + * The first thre values are address values as address-cells is 3 + * The first value is the bus number in bits 31-16 (normal 0 because masked out) + * Bits 15-8 are the devfn (this is the IDSEL Line shift 3 bits to the left IDSEL AD15 is 0x78) + * Bis 7-0 are unused set to 0 and mask out with the interrupt-mask value + * The following two values should be 0 and masked out + * The fourth value is the interrupt bis from PCI configuration header (one value as interrupt-cells is 1) + * The last three values are the interrupt this interrupt is connected to. + * First interrupt controller node, then the number and last the flags (8 means level low) */ + interrupt-map = < + /* IDSEL 0x10 - first PCI slot */ + 0x8000 0x0 0x0 0x1 &ipic 18 0x8 + 0x8000 0x0 0x0 0x2 &ipic 19 0x8 + 0x8000 0x0 0x0 0x3 &ipic 20 0x8 + 0x8000 0x0 0x0 0x3 &ipic 21 0x8 + + /* IDSEL 0x11 - Second PCI slot */ + 0x8800 0x0 0x0 0x1 &ipic 19 0x8 + 0x8800 0x0 0x0 0x2 &ipic 20 0x8 + 0x8800 0x0 0x0 0x3 &ipic 21 0x8 + 0x8800 0x0 0x0 0x4 &ipic 18 0x8 + + /* IDSEL 0x12 - USB controller */ + 0x9000 0x0 0x0 0x1 &ipic 21 0x8>; + interrupt-parent = <&ipic>; + interrupts = <66 0x8>; + bus-range = <0x0 0x0>; + ranges = <0x42000000 0 0xC0000000 0xC0000000 0 0x10000000 + 0x02000000 0 0xD0000000 0xD0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; + clock-frequency = <0>; // from bootloader + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe0008500 0x100 /* internal registers */ + 0xe0008300 0x8>; /* config space access registers */ + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; + + pci1: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000>; + ranges = <0x02000000 0 0x40000000 0x40000000 0 0x10000000 + 0x01000000 0 0x00000000 0xe3100000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0x0 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + clock-frequency = <0>; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0x40000000 + 0x02000000 0 0x40000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; + + pci2: pcie@e000a000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; + reg = <0xe000a000 0x00001000>; + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000 + 0x01000000 0 0x00000000 0xe3180000 0 0x00800000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 2 8 + 0 0 0 2 &ipic 2 8 + 0 0 0 3 &ipic 2 8 + 0 0 0 4 &ipic 2 8>; + clock-frequency = <0>; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0x60000000 + 0x02000000 0 0x60000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; +};
diff --git a/arch/powerpc/configs/83xx/ib8315_defconfig b/arch/powerpc/configs/83xx/ib8315_defconfig
new file mode 100644
index 0000000..5788130
--- /dev/null
+++ b/arch/powerpc/configs/83xx/ib8315_defconfig@@ -0,0 +1,102 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +# CONFIG_EPOLL is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_EFI_PARTITION is not set +# CONFIG_PPC_CHRP is not set +# CONFIG_PPC_PMAC is not set +CONFIG_PPC_83xx=y +CONFIG_TQM8315=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEASPM is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=32768 +CONFIG_EEPROM_AT24=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_ATA=y +CONFIG_SATA_FSL=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_3COM is not set +CONFIG_GIANFAR=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MPC=y +CONFIG_SENSORS_LM75=y +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_FSL=y +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +CONFIG_USB_STORAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_MSDOS_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_PRINTK_TIME=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 670a033..1d280d5 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig@@ -24,6 +24,13 @@ config MPC831x_RDB help This option enables support for the MPC8313 RDB and MPC8315 RDB boards. +config TQM8315 + bool "TQM8315 Board" + select DEFAULT_UIMAGE + select PPC_MPC831x + help + This option enables support for the TQM8315 processor board. +
config MPC832x_MDS
bool "Freescale MPC832x MDS"
select DEFAULT_UIMAGEdiff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index ed95bfc..05524f1 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile@@ -6,6 +6,7 @@ obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.oobj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o +obj-$(CONFIG_TQM8315) += tqm8315.o obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
diff --git a/arch/powerpc/platforms/83xx/tqm8315.c b/arch/powerpc/platforms/83xx/tqm8315.c
new file mode 100644
index 0000000..04c106a
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/tqm8315.c@@ -0,0 +1,137 @@ +/* + * arch/powerpc/platforms/83xx/tqm8315.c + * + * Description: TQM8315 board specific routines. + * + * Author: Oliver Weber <o.weber@gateware.de> + * Copyright (C) TQ Components 2009. + * + * This file is based on mpc831x_rdb.c, + * Author: Lo Wlison <r43300@freescale.com> + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/pci.h> +#include <linux/of_platform.h> + +#include <linux/time.h> +#include <asm/ipic.h> +#include <asm/udbg.h> +#include <sysdev/fsl_pci.h> +#include <sysdev/fsl_soc.h> + +#include "mpc83xx.h" + +#define MPC8315_SATA_PHYCTRL_REG_OFFSET 0x15C +#define PHYCTRLCFG_REFCLK_MASK 0x00000070 +#define PHYCTRLCFG_REFCLK_50MHZ 0x00000050 +#define PHYCTRLCFG_REFCLK_75MHZ 0x00000000 +#define PHYCTRLCFG_REFCLK_100MHZ 0x00000060 +#define PHYCTRLCFG_REFCLK_125MHZ 0x00000070 +#define PHYCTRLCFG_REFCLK_150MHZ 0x00000020 + + +#ifdef CONFIG_SATA_FSL +void init_mpc8315_sata_phy(void) +{ + u32 val32; + void __iomem *immap; + + immap = ioremap(get_immrbase() + 0x18000, 0x1000); + if (immap == NULL) + return; + + /* Configure PHY for 125 MHz reference clock */ + val32 = ioread32(immap + MPC8315_SATA_PHYCTRL_REG_OFFSET); + val32 &= ~PHYCTRLCFG_REFCLK_MASK; + val32 |= PHYCTRLCFG_REFCLK_125MHZ; + iowrite32(val32, immap + MPC8315_SATA_PHYCTRL_REG_OFFSET); + + iounmap(immap); +} +#endif + +/* + * Setup the architecture + */ +static void __init tqm8315_setup_arch(void) +{ +#ifdef CONFIG_PCI + struct device_node *np; +#endif + + if (ppc_md.progress) + ppc_md.progress("tqm8315_setup_arch()", 0); + +#ifdef CONFIG_PCI + for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") + mpc83xx_add_bridge(np); + for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie") + mpc83xx_add_bridge(np); +#endif + mpc831x_usb_cfg(); + +#ifdef CONFIG_SATA_FSL + init_mpc8315_sata_phy(); +#endif +} + +static void __init tqm8315_init_IRQ(void) +{ + struct device_node *np; + + np = of_find_node_by_type(NULL, "ipic"); + if (!np) + return; + + ipic_init(np, 0); + + /* Initialize the default interrupt mapping priorities, + * in case the boot rom changed something on us. + */ + ipic_set_default_priority(); +} + +/* + * Called very early, MMU is off, device-tree isn't unflattened + */ +static int __init tqm8315_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "TQM8315") + || of_flat_dt_is_compatible(root, "fsl,tqm8315"); +} + +static struct of_device_id __initdata of_bus_ids[] = { + {.compatible = "simple-bus"}, + {.compatible = "gianfar"}, + {}, +}; + +static int __init declare_of_platform_devices(void) +{ + of_platform_bus_probe(NULL, of_bus_ids, NULL); + return 0; +} +machine_device_initcall(tqm8315, declare_of_platform_devices); + +define_machine(tqm8315) { + .name = "TQM8315", + .probe = tqm8315_probe, + .setup_arch = tqm8315_setup_arch, + .init_IRQ = tqm8315_init_IRQ, + .get_irq = ipic_get_irq, + .restart = mpc83xx_restart, + .time_init = mpc83xx_time_init, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif +}; --
1.7.11.7