[PATCH] powerpc/dts: Added aliased MSIIR register address to MSI node in dts

From: Diana CRACIUN <redacted>

The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:

e.g. reg = <0x41600 0x200 0x44140 4>;

The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.

Signed-off-by: Diana CRACIUN <redacted>
---
 .../devicetree/bindings/powerpc/fsl/msi-pic.txt    |    6 ++++--
 arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi          |    6 +++---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5d586e1..5693877 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt

@@ -6,8 +6,10 @@ Required properties:
   etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
   the parent type.
 
-- reg : should contain the address and the length of the shared message
-  interrupt register set.
+- reg : It may contain one or two regions. The first region should contain
+  the address and the length of the shared message interrupt register set.
+  The second region should contain the address of aliased MSIIR register for
+  platforms that have such an alias.
 
 - msi-available-ranges: use <start count> style section to define which
   msi interrupt can be used in the 256 msi interrupts. This property is

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6..08f4227 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi

@@ -53,7 +53,7 @@ timer@41100 {
 
 msi0: msi@41600 {
 	compatible = "fsl,mpic-msi";
-	reg = <0x41600 0x200>;
+	reg = <0x41600 0x200 0x44140 4>;
 	msi-available-ranges = <0 0x100>;
 	interrupts = <
 		0xe0 0 0 0

@@ -68,7 +68,7 @@ msi0: msi@41600 {
 
 msi1: msi@41800 {
 	compatible = "fsl,mpic-msi";
-	reg = <0x41800 0x200>;
+	reg = <0x41800 0x200 0x45140 4>;
 	msi-available-ranges = <0 0x100>;
 	interrupts = <
 		0xe8 0 0 0

@@ -83,7 +83,7 @@ msi1: msi@41800 {
 
 msi2: msi@41a00 {
 	compatible = "fsl,mpic-msi";
-	reg = <0x41a00 0x200>;
+	reg = <0x41a00 0x200 0x46140 4>;
 	msi-available-ranges = <0 0x100>;
 	interrupts = <
 		0xf0 0 0 0

-- 
1.7.3.4

On Feb 1, 2012, at 9:50 AM, Diana Craciun wrote:

From: Diana CRACIUN <redacted>
=20
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:
=20
e.g. reg =3D <0x41600 0x200 0x44140 4>;
=20
The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.
=20
Signed-off-by: Diana CRACIUN <redacted>
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt    |    6 ++++--
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi          |    6 +++---
2 files changed, 7 insertions(+), 5 deletions(-)

Why, we should only use one of the register regions.  The second region =
was added to allow for 4k separation and thus PAMU protection.  Not sure =
what listed both regions gets us.

- k=

On 03/16/2012 02:32 PM, Kumar Gala wrote:

On Feb 1, 2012, at 9:50 AM, Diana Craciun wrote:

quoted

From: Diana CRACIUN <redacted>

The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:

e.g. reg = <0x41600 0x200 0x44140 4>;

The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.

Signed-off-by: Diana CRACIUN <redacted>
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt    |    6 ++++--
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi          |    6 +++---
2 files changed, 7 insertions(+), 5 deletions(-)

Why, we should only use one of the register regions.  The second region was added to allow for 4k separation and thus PAMU protection.  Not sure what listed both regions gets us.

We list both because the hardware has both.  Device tree describes the
hardware; it doesn't tell you how to use it.

Plus, the separte 4K page has only the MSIIRn register, not the other
MSI registers.  So we still need the first resource.

The second resource will probably not be used by Linux at the moment,
but it used by Topaz, and it may be used by KVM/VFIO in the future.

-Scott