[PATCH 06/13] PCI, powerpc: Register busn_res for root buses

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <redacted>
Cc: linuxppc-dev@lists.ozlabs.org
---
 arch/powerpc/kernel/pci-common.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index cce98d7..501f29b 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c

@@ -1732,6 +1732,8 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
 	bus->secondary = hose->first_busno;
 	hose->bus = bus;
 
+	pci_bus_insert_busn_res(bus, hose->first_busno, hose->last_busno);
+
 	/* Get probe mode and perform scan */
 	mode = PCI_PROBE_NORMAL;
 	if (node && ppc_md.pci_probe_mode)

@@ -1742,8 +1744,11 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
 		of_scan_bus(node, bus);
 	}
 
-	if (mode == PCI_PROBE_NORMAL)
+	if (mode == PCI_PROBE_NORMAL) {
+		pci_bus_update_busn_res_end(bus, 255);
 		hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
+		pci_bus_update_busn_res_end(bus, bus->subordinate);
+	}
 
 	/* Platform gets a chance to do some global fixups before
 	 * we proceed to resource allocation

-- 
1.7.7

On Fri, Jan 27, 2012 at 6:49 PM, Yinghai Lu [off-list ref] wrote:

ommon.c

er *hose)

=A0 =A0 =A0 =A0bus->secondary =3D hose->first_busno;
=A0 =A0 =A0 =A0hose->bus =3D bus;

+ =A0 =A0 =A0 pci_bus_insert_busn_res(bus, hose->first_busno, hose->last_=

busno);

The pci_create_root_bus() call is a few lines above this.  So this is
a case of "create the root bus" followed by "fix something that's
wrong with the bus we just created."  I'm trying to get rid of that
pattern because it's just an opportunity for bugs.  I'd rather create
the root bus with all the information it needs up front.

And pci_bus_insert_busn_res() is not really architecture-specific, so
I'd like this better if that call were done in the PCI core somewhere.

ler *hose)

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0of_scan_bus(node, bus);
=A0 =A0 =A0 =A0}

- =A0 =A0 =A0 if (mode =3D=3D PCI_PROBE_NORMAL)
+ =A0 =A0 =A0 if (mode =3D=3D PCI_PROBE_NORMAL) {
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 pci_bus_update_busn_res_end(bus, 255);
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0hose->last_busno =3D bus->subordinate =3D =

pci_scan_child_bus(bus);

+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 pci_bus_update_busn_res_end(bus, bus->subor=

dinate);

+ =A0 =A0 =A0 }

=A0 =A0 =A0 =A0/* Platform gets a chance to do some global fixups before
=A0 =A0 =A0 =A0 * we proceed to resource allocation
--
1.7.7