[PATCH v11 3/6] flexcan: Fix up fsl-flexcan device tree binding.

This patch cleans up the documentation of the device-tree binding for
the Flexcan devices on Freescale's PowerPC and ARM cores. Extra
properties are not used by the driver so we are removing them.

Signed-off-by: Robin Holt <redacted>
To: Marc Kleine-Budde <mkl@pengutronix.de>,
To: Wolfgang Grandegger <redacted>,
To: U Bhaskar-B22300 <redacted>
To: Scott Wood <redacted>
To: Grant Likely <redacted>
To: Kumar Gala <redacted>
Cc: socketcan-core@lists.berlios.de,
Cc: netdev@vger.kernel.org,
Cc: PPC list <redacted>
Cc: devicetree-discuss@lists.ozlabs.org
---
 .../devicetree/bindings/net/can/fsl-flexcan.txt    |   69 ++++---------------
 arch/powerpc/boot/dts/p1010rdb.dts                 |   10 +--
 arch/powerpc/boot/dts/p1010si.dtsi                 |   10 +--
 3 files changed, 21 insertions(+), 68 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 1a729f0..c78dcbb 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt

@@ -1,61 +1,22 @@
-CAN Device Tree Bindings
-------------------------
-2011 Freescale Semiconductor, Inc.
+Flexcan CAN contoller on Freescale's ARM and PowerPC processors
 
-fsl,flexcan-v1.0 nodes
------------------------
-In addition to the required compatible-, reg- and interrupt-properties, you can
-also specify which clock source shall be used for the controller.
+Required properties:
 
-CPI Clock- Can Protocol Interface Clock
-	This CLK_SRC bit of CTRL(control register) selects the clock source to
-	the CAN Protocol Interface(CPI) to be either the peripheral clock
-	(driven by the PLL) or the crystal oscillator clock. The selected clock
-	is the one fed to the prescaler to generate the Serial Clock (Sclock).
-	The PRESDIV field of CTRL(control register) controls a prescaler that
-	generates the Serial Clock (Sclock), whose period defines the
-	time quantum used to compose the CAN waveform.
+- compatible : Should be "fsl,<processor>-flexcan" and "fsl,flexcan"
 
-Can Engine Clock Source
-	There are two sources for CAN clock
-	- Platform Clock  It represents the bus clock
-	- Oscillator Clock
+  An implementation should also claim any of the following compatibles
+  that it is fully backwards compatible with:
 
-	Peripheral Clock (PLL)
-	--------------
-		     |
-		    ---------		      -------------
-		    |       |CPI Clock	      | Prescaler |       Sclock
-		    |       |---------------->| (1.. 256) |------------>
-		    ---------		      -------------
-                     |  |
-	--------------  ---------------------CLK_SRC
-	Oscillator Clock
+  - fsl,p1010-flexcan
 
-- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
-			     the peripheral clock. PLL clock is fed to the
-			     prescaler to generate the Serial Clock (Sclock).
-			     Valid values are "oscillator" and "platform"
-			     "oscillator": CAN engine clock source is oscillator clock.
-			     "platform" The CAN engine clock source is the bus clock
-		             (platform clock).
+- reg : Offset and length of the register set for this device
+- interrupts : Interrupt tuple for this device
 
-- fsl,flexcan-clock-divider : for the reference and system clock, an additional
-			      clock divider can be specified.
-- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
+Example:
 
-Note:
-	- v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
-	- P1010 does not have oscillator as the Clock Source.So the default
-	  Clock Source is platform clock.
-Examples:
-
-	can0@1c000 {
-		compatible = "fsl,flexcan-v1.0";
-		reg = <0x1c000 0x1000>;
-		interrupts = <48 0x2>;
-		interrupt-parent = <&mpic>;
-		fsl,flexcan-clock-source = "platform";
-		fsl,flexcan-clock-divider = <2>;
-		clock-frequency = <fixed by u-boot>;
-	};
+  can@1c000 {
+          compatible = "fsl,p1010-flexcan", "fsl,flexcan";
+          reg = <0x1c000 0x1000>;
+          interrupts = <48 0x2>;
+          interrupt-parent = <&mpic>;
+  };

diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
index 6b33b73..d6c669c 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ b/arch/powerpc/boot/dts/p1010rdb.dts

@@ -23,6 +23,8 @@
 		ethernet2 = &enet2;
 		pci0 = &pci0;
 		pci1 = &pci1;
+		can0 = &can0;
+		can1 = &can1;
 	};
 
 	memory {

@@ -169,14 +171,6 @@
 			};
 		};
 
-		can0@1c000 {
-			fsl,flexcan-clock-source = "platform";
-		};
-
-		can1@1d000 {
-			fsl,flexcan-clock-source = "platform";
-		};
-
 		usb@22000 {
 			phy_type = "utmi";
 		};

diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
index 7f51104..f00076b 100644
--- a/arch/powerpc/boot/dts/p1010si.dtsi
+++ b/arch/powerpc/boot/dts/p1010si.dtsi

@@ -140,20 +140,18 @@
 			interrupt-parent = <&mpic>;
 		};
 
-		can0@1c000 {
-			compatible = "fsl,flexcan-v1.0";
+		can0: can@1c000 {
+			compatible = "fsl,p1010-flexcan", "fsl,flexcan";
 			reg = <0x1c000 0x1000>;
 			interrupts = <48 0x2>;
 			interrupt-parent = <&mpic>;
-			fsl,flexcan-clock-divider = <2>;
 		};
 
-		can1@1d000 {
-			compatible = "fsl,flexcan-v1.0";
+		can1: can@1d000 {
+			compatible = "fsl,p1010-flexcan", "fsl,flexcan";
 			reg = <0x1d000 0x1000>;
 			interrupts = <61 0x2>;
 			interrupt-parent = <&mpic>;
-			fsl,flexcan-clock-divider = <2>;
 		};
 
 		L2: l2-cache-controller@20000 {

-- 
1.7.2.1

On Thu, Aug 11, 2011 at 10:07 AM, Robin Holt [off-list ref] wrote:

This patch cleans up the documentation of the device-tree binding for
the Flexcan devices on Freescale's PowerPC and ARM cores. Extra
properties are not used by the driver so we are removing them.

Signed-off-by: Robin Holt <redacted>
To: Marc Kleine-Budde <mkl@pengutronix.de>,
To: Wolfgang Grandegger <redacted>,
To: U Bhaskar-B22300 <redacted>
To: Scott Wood <redacted>
To: Grant Likely <redacted>
To: Kumar Gala <redacted>
Cc: socketcan-core@lists.berlios.de,
Cc: netdev@vger.kernel.org,
Cc: PPC list <redacted>
Cc: devicetree-discuss@lists.ozlabs.org
---
=A0.../devicetree/bindings/net/can/fsl-flexcan.txt =A0 =A0| =A0 69 ++++--=

-------------

=A0arch/powerpc/boot/dts/p1010rdb.dts =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =

=A0 10 +--

=A0arch/powerpc/boot/dts/p1010si.dtsi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =

=A0 10 +--

Documentation/devicetree/bindings/net/can/fsl-flexcan.txt

you can

-also specify which clock source shall be used for the controller.
+Required properties:

-CPI Clock- Can Protocol Interface Clock
- =A0 =A0 =A0 This CLK_SRC bit of CTRL(control register) selects the cloc=

k source to

- =A0 =A0 =A0 the CAN Protocol Interface(CPI) to be either the peripheral=

 clock

- =A0 =A0 =A0 (driven by the PLL) or the crystal oscillator clock. The se=

lected clock

- =A0 =A0 =A0 is the one fed to the prescaler to generate the Serial Cloc=

k (Sclock).

- =A0 =A0 =A0 The PRESDIV field of CTRL(control register) controls a pres=

caler that

- =A0 =A0 =A0 generates the Serial Clock (Sclock), whose period defines t=

he

- =A0 =A0 =A0 time quantum used to compose the CAN waveform.
+- compatible : Should be "fsl,<processor>-flexcan" and "fsl,flexcan"

Don't do this.  "fsl,flexcan" is far too generic.  Be specific to the
soc part number or the ip core implementation version.

-Can Engine Clock Source
- =A0 =A0 =A0 There are two sources for CAN clock
- =A0 =A0 =A0 - Platform Clock =A0It represents the bus clock
- =A0 =A0 =A0 - Oscillator Clock
+ =A0An implementation should also claim any of the following compatibles
+ =A0that it is fully backwards compatible with:

- =A0 =A0 =A0 Peripheral Clock (PLL)
- =A0 =A0 =A0 --------------
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --------- =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 -------------

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 |CPI Clock =A0 =A0 =

=A0 =A0| Prescaler | =A0 =A0 =A0 Sclock

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 |---------------->| (=

1.. 256) |------------>

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --------- =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 -------------

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0|
- =A0 =A0 =A0 -------------- =A0---------------------CLK_SRC
- =A0 =A0 =A0 Oscillator Clock
+ =A0- fsl,p1010-flexcan

-- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selec=

ts

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0the peripheral c=

lock. PLL clock is fed to the

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0prescaler to gen=

erate the Serial Clock (Sclock).

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Valid values are=

 "oscillator" and "platform"

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"oscillator": CA=

N engine clock source is oscillator clock.

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"platform" The C=

AN engine clock source is the bus clock

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(platform clock)=

.

+- reg : Offset and length of the register set for this device
+- interrupts : Interrupt tuple for this device

-- fsl,flexcan-clock-divider : for the reference and system clock, an add=

itional

- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock divider c=

an be specified.

-- clock-frequency: frequency required to calculate the bitrate for FlexC=

AN.

+Example:

-Note:
- =A0 =A0 =A0 - v1.0 of flexcan-v1.0 represent the IP block version for P=

1010 SOC.

- =A0 =A0 =A0 - P1010 does not have oscillator as the Clock Source.So the=

 default

- =A0 =A0 =A0 =A0 Clock Source is platform clock.
-Examples:
-
- =A0 =A0 =A0 can0@1c000 {
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,flexcan-v1.0";
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1c000 0x1000>;
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 interrupts =3D <48 0x2>;
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 interrupt-parent =3D <&mpic>;
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl,flexcan-clock-source =3D "platform";
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl,flexcan-clock-divider =3D <2>;
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock-frequency =3D <fixed by u-boot>;
- =A0 =A0 =A0 };
+ =A0can@1c000 {
+ =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,p1010-flexcan", "fsl,flexcan";
+ =A0 =A0 =A0 =A0 =A0reg =3D <0x1c000 0x1000>;
+ =A0 =A0 =A0 =A0 =A0interrupts =3D <48 0x2>;
+ =A0 =A0 =A0 =A0 =A0interrupt-parent =3D <&mpic>;
+ =A0};

The diffstat for this patch looks too big because the whitespace has
changed.  Try to restrict whitespace changes so that the patch is
friendly to reviewers.

g.