mpc5121 Power Managment errata.

I have a bit of a problem with arch/powerpc/platforms/512x/mpc512x_pm.c
Since this one is not included in mainline (yet) I have attached it 

Now I have a number of questions and one mystery.

1: why relocate the code ?? is there a reason why the code must be
located at address 0 

http://www.bitshrine.org/gpp/linux-2.6.24.6-mpc5121-99-PM-alternate-external-int-vector.patch

say that this is due to a bug in the PMC module with status bits. Could
this not be worked around by avoiding modifying the exception handler
and just taken care of by C code in ipic.c

2: does it work ??? 
I ask since it do self modifying code but no invalidation of the
instruction cache.


Mystery: If I fix the cache issue with the code and force store of data
with dcbst and invalidate with icbi. I get a very unreliable resume
function that often end up in machine check all over the place 

This machine check also happens on unmodified version but much much more
seldom. I'm just now running some test on a system that only patch this
in once and thus always run with this workaround without constantly
modifying the exception handler . but I wont know if it makes a
difference until tomorrow.


I have inserted this code in the end of both 
mpc5121_copy_pmcclr
mpc5121_reinstall_handler
Is there some reason why this would not work ?? 
-----------------------------------------
	/*
	dcbst |update memory
	sync |wait for update
	icbi |remove (invalidate) copy in instruction cache
	isync |remove copy in own instruction buffer
	*/

	lis	r3, CONFIG_KERNEL_START@h
	ori	r3, r3, CONFIG_KERNEL_START@l

	/* flush and invalidate from 0 to 0x600 */
	li	r5, 0x0
	li	r4, 0x600/L1_CACHE_BYTES
	mtctr	r4
1:
	dcbst	r5,r3
	sync
	icbi	r5,r3
	isync
	addi	r5, r5, L1_CACHE_BYTES    /* Next line, please */

	bdnz	1b
	sync
	isync