[PATCH] [POWERPC] mpic: deal with bogus NIRQ in Feature Reporting Register

Some chips (like the SoCs from Freescale) report the wrong value in NIRQ
and this causes issues if its doesn't match or exceed the value of
irq_count.

Add a flag that board code can set to just use irq_count instead of
FRR[NIRQ].  Eventually we'll add a device tree property with the number
of sources.

Signed-off-by: Kumar Gala <redacted>
---
 arch/powerpc/sysdev/mpic.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 8619f2a..4530b38 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c

@@ -1144,9 +1144,9 @@ struct mpic * __init mpic_alloc(struct device_node *node,
 	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
 			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
 	if (isu_size == 0)
-		mpic->num_sources =
+		mpic->num_sources = max(mpic->irq_count,
 			((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
-			 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
+			 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1);

 	/* Map the per-CPU registers */
 	for (i = 0; i < mpic->num_cpus; i++) {

-- 
1.5.4.5

On Wed, May 21, 2008 at 03:57:55PM -0500, Kumar Gala wrote:

Some chips (like the SoCs from Freescale) report the wrong value in NIRQ
and this causes issues if its doesn't match or exceed the value of
irq_count.

Is it really wrong, or just not accounting for the gap between external
and internal interrupts?

-Scott

On May 21, 2008, at 5:11 PM, Scott Wood wrote:

On Wed, May 21, 2008 at 03:57:55PM -0500, Kumar Gala wrote:

quoted

Some chips (like the SoCs from Freescale) report the wrong value in NIRQ
and this causes issues if its doesn't match or exceed the value of
irq_count.

Is it really wrong, or just not accounting for the gap between external
and internal interrupts?

I consider it wrong by my interpretation of the open-pic spec.

The spec says:

Num IRQ Sources:  The number of highest IRQ source supported.  For instance, in a 32 source
implementation, this value will be 31.  This allows support of a maximum of 2048 interrupt sources.

(Interrupt Sources are in the 0x10000 to 0x1ffff range).

So for something like 8572, the top most interrupt source is at 0x1CE0.  So I'd take that to mean NIRQs should be 231. (0x1CE0 / 0x20 - 1).  NIRQS reports 107.

- k