Hi all,=20
The engineers of Freescale have recognized a problem in the PSC SPI =
Slave Select signal when there is a heavy ethernet loading. Textually =
they say:
" I have tested the MPC5200B FEC and PSC6 SPI.=20
You are right. If there is heavy Ethernet loading, the PSC SPI can stop =
during transmission with SS goes high.
Use a general-purpose output as SPI slave select signal instead PSC SPI =
SS signal.
Factory is informed about similar incorrect behaviour of the PSC SPI =
slave select."
We have repeated the error in three scenarios:
In our MPC5200B custom board with a Denx 2.4.25 kernel.
In a Lite5200B with a Denx 2.4.25 kernel.
In a Lite5200B with the freescale bsp: =
mpc5200_lite5200b_20070203_ltib-rc4. It's a 2.6.16 kernel version.
We have checked the PSC3 and PSC6 and the behaviour is the same.
So, it seems is a chip's bug and we must avoid to use the SS signal with =
the PSC SPI if we want to communicate by ethernet. I think it's a =
probabilistic error and in case there is some traffic in ethernet and a =
transmission by SPI at the same time it could happen.
Best regards,
Txema L=F3pez.
=09
=09
=09
On Monday 28 January 2008 09:37, TXEMA LOPEZ wrote:
The engineers of Freescale have recognized a problem in the PSC SPI Slave
Select signal when there is a heavy ethernet loading. Textually they say:
" I have tested the MPC5200B FEC and PSC6 SPI.
You are right. If there is heavy Ethernet loading, the PSC SPI can stop
during transmission with SS goes high. Use a general-purpose output as SPI
slave select signal instead PSC SPI SS signal. Factory is informed about
similar incorrect behaviour of the PSC SPI slave select."
We have repeated the error in three scenarios:
In our MPC5200B custom board with a Denx 2.4.25 kernel.
In a Lite5200B with a Denx 2.4.25 kernel.
In a Lite5200B with the freescale bsp:
mpc5200_lite5200b_20070203_ltib-rc4. It's a 2.6.16 kernel version.
We have checked the PSC3 and PSC6 and the behaviour is the same.
So, it seems is a chip's bug and we must avoid to use the SS signal with
the PSC SPI if we want to communicate by ethernet. I think it's a
probabilistic error and in case there is some traffic in ethernet and a
transmission by SPI at the same time it could happen.
There seems also another bug: If the PSC based SPI unit runs as SPI slave, =
and=20
some data in the send FIFO waits for transmission, the MISO line is active=
=20
even if SS input is high and blocks the bus. It does not happen, of the sen=
d=20
=46IFO is empty.
JB
=2D-=20
Dipl.-Ing. Juergen Beisert | http://www.pengutronix.de
=A0Pengutronix - Linux Solutions for Science and Industry
=A0 Handelsregister: Amtsgericht Hildesheim, HRA 2686
=A0 =A0 =A0 Vertretung Sued/Muenchen, Germany
Phone: +49-8766-939 228 | Fax: +49-5121-206917-9