Re: Linux for ml310

Hi again

I tried my compiled kernel this morning.
I loaded my Bitstream onto the FPGA, then the zImage.elf via xmd: dow zIma=
ge.elf.
After I typed "run" I got foolowing message on an Terminal:
------------------------------------------------------------------------
loaded at:     00400000 004F219C
board data at: 004F0120 004F019C
relocated to:  00404048 004040C4
zimage at:     00404E39 004EF931
avail ram:     004F3000 10000000

Linux/PPC load: console=3DttyS0,9600
Uncompressing Linux...done.
Now booting the kernel

------------------------------------------------------------------------
Doesn't look that bad I think. ;)
The Question I have is of course why he stops there.
Is it why He can't find a rootfs=3F
Or would he say this in that case.
I found someone with an similar Problem:
http://lists.ppckernel.org/pipermail/ppckernel/2006-May/000026.html
but I already use the xparameters=5Fml310 from my BSP.
Where must I look for the error=3F
There where some warnings when I compiled the kernel. Is this ok=3F

Greets & THX
Joachim

PS: My xparameters=5Fml310.h
--------------------------------------------------------------------------=
----------------------------------------------
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 9.1.02 EDK=5FJ=5FSP2.4
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc.  All rights reserved.=20
*=20
* Description: Driver parameters
*
*******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR=5FXUARTLITE=5FNUM=5FINSTANCES 1

/* Definitions for peripheral RS232=5FUART */
#define XPAR=5FRS232=5FUART=5FBASEADDR 0x40600000
#define XPAR=5FRS232=5FUART=5FHIGHADDR 0x4060FFFF
#define XPAR=5FRS232=5FUART=5FDEVICE=5FID 0
#define XPAR=5FRS232=5FUART=5FBAUDRATE 9600
#define XPAR=5FRS232=5FUART=5FUSE=5FPARITY 0
#define XPAR=5FRS232=5FUART=5FODD=5FPARITY 0
#define XPAR=5FRS232=5FUART=5FDATA=5FBITS 8


/******************************************************************/

/* Definitions for driver SPI */
#define XPAR=5FXSPI=5FNUM=5FINSTANCES 1

/* Definitions for peripheral SPI=5FEEPROM */
#define XPAR=5FSPI=5FEEPROM=5FBASEADDR 0x4B308000
#define XPAR=5FSPI=5FEEPROM=5FHIGHADDR 0x4B30807F
#define XPAR=5FSPI=5FEEPROM=5FDEVICE=5FID 0
#define XPAR=5FSPI=5FEEPROM=5FFIFO=5FEXIST 1
#define XPAR=5FSPI=5FEEPROM=5FSPI=5FSLAVE=5FONLY 0
#define XPAR=5FSPI=5FEEPROM=5FNUM=5FSS=5FBITS 1


/******************************************************************/

/* Definitions for driver PCI */
#define XPAR=5FXPCI=5FNUM=5FINSTANCES 1

/* Definitions for peripheral PCI32=5FBRIDGE */
#define XPAR=5FPCI32=5FBRIDGE=5FDEVICE=5FID 0
#define XPAR=5FPCI32=5FBRIDGE=5FBASEADDR 0x42600000
#define XPAR=5FPCI32=5FBRIDGE=5FHIGHADDR 0x4260FFFF
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5F0 0x00000000
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FLEN=5F0 7
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR2IPIF=5F0 0
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FENDIAN=5FTRANSLATE=5FEN=5F0 0
#define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FPREFETCH=5F0 1
#define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FSPACETYPE=5F0 1
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5F1 0xffffffff
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FLEN=5F1 20
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR2IPIF=5F1 0
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FENDIAN=5FTRANSLATE=5FEN=5F1 0
#define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FPREFETCH=5F1 1
#define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FSPACETYPE=5F1 1
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5F2 0xffffffff
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FLEN=5F2 20
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR2IPIF=5F2 0
#define XPAR=5FPCI32=5FBRIDGE=5FPCIBAR=5FENDIAN=5FTRANSLATE=5FEN=5F2 0
#define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FPREFETCH=5F2 1
#define XPAR=5FPCI32=5FBRIDGE=5FPCI=5FSPACETYPE=5F2 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F0 0x60000000
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F0 0x7fffffff
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F0 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F0 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F0 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F0 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F1 0x54000000
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F1 0x57ffffff
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F1 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F1 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F1 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F1 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F2 0xffffffff
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F2 0x00000000
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F2 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F2 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F2 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F2 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F3 0xffffffff
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F3 0x00000000
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F3 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F3 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F3 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F3 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F4 0xffffffff
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F4 0x00000000
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F4 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F4 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F4 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F4 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5F5 0xffffffff
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FHIGHADDR=5F5 0x00000000
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR2PCI=5F5 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIFBAR=5FENDIAN=5FTRANSLATE=5FEN=5F5 0
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FPREFETCH=5F5 1
#define XPAR=5FPCI32=5FBRIDGE=5FIPIF=5FSPACETYPE=5F5 1
#define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FBASEADDR 0xFFFFFFFF
#define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FHIGHADDR 0x00000000
#define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FCHAN=5FTYPE 9
#define XPAR=5FPCI32=5FBRIDGE=5FDMA=5FLENGTH=5FWIDTH 13
#define XPAR=5FPCI32=5FBRIDGE=5FBRIDGE=5FIDSEL=5FADDR=5FBIT 16


/******************************************************************/

#define XPAR=5FXSYSACE=5FMEM=5FWIDTH 8
/* Definitions for driver SYSACE */
#define XPAR=5FXSYSACE=5FNUM=5FINSTANCES 1

/* Definitions for peripheral SYSACE=5FCOMPACTFLASH */
#define XPAR=5FSYSACE=5FCOMPACTFLASH=5FBASEADDR 0x41800000
#define XPAR=5FSYSACE=5FCOMPACTFLASH=5FHIGHADDR 0x4180FFFF
#define XPAR=5FSYSACE=5FCOMPACTFLASH=5FDEVICE=5FID 0
#define XPAR=5FSYSACE=5FCOMPACTFLASH=5FMEM=5FWIDTH 8


/******************************************************************/

#define XPAR=5FINTC=5FMAX=5FNUM=5FINTR=5FINPUTS 12
#define XPAR=5FXINTC=5FHAS=5FIPR 1
#define XPAR=5FXINTC=5FUSE=5FDCR 0
/* Definitions for driver INTC */
#define XPAR=5FXINTC=5FNUM=5FINSTANCES 1

/* Definitions for peripheral OPB=5FINTC=5F0 */
#define XPAR=5FOPB=5FINTC=5F0=5FBASEADDR 0x41200000
#define XPAR=5FOPB=5FINTC=5F0=5FHIGHADDR 0x4120FFFF
#define XPAR=5FOPB=5FINTC=5F0=5FDEVICE=5FID 0
#define XPAR=5FOPB=5FINTC=5F0=5FKIND=5FOF=5FINTR 0x00000C00


/******************************************************************/

#define XPAR=5FINTC=5FSINGLE=5FBASEADDR 0x41200000
#define XPAR=5FINTC=5FSINGLE=5FHIGHADDR 0x4120FFFF
#define XPAR=5FINTC=5FSINGLE=5FDEVICE=5FID XPAR=5FOPB=5FINTC=5F0=5FDEVICE=5FID
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FSBR=5FINT=5FMASK 0X000001
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FSBR=5FINT=5FINTR 0
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTF=5FMASK 0X000002
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTF=5FINTR 1
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTE=5FMASK 0X000004
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTE=5FINTR 2
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTD=5FMASK 0X000008
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTD=5FINTR 3
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTC=5FMASK 0X000010
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTC=5FINTR 4
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTB=5FMASK 0X000020
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTB=5FINTR 5
#define XPAR=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTA=5FMASK 0X000040
#define XPAR=5FOPB=5FINTC=5F0=5FSYSTEM=5FFPGA=5F0=5FPCI32=5FBRIDGE=5FPCI=5FINTA=5FINTR 6
#define XPAR=5FSYSACE=5FCOMPACTFLASH=5FSYSACE=5FIRQ=5FMASK 0X000080
#define XPAR=5FOPB=5FINTC=5F0=5FSYSACE=5FCOMPACTFLASH=5FSYSACE=5FIRQ=5FINTR 7
#define XPAR=5FPCI32=5FBRIDGE=5FIP2INTC=5FIRPT=5FMASK 0X000100
#define XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIRPT=5FINTR 8
#define XPAR=5FSPI=5FEEPROM=5FIP2INTC=5FIRPT=5FMASK 0X000200
#define XPAR=5FOPB=5FINTC=5F0=5FSPI=5FEEPROM=5FIP2INTC=5FIRPT=5FINTR 9
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FIP2INTC=5FIRPT=5FMASK 0X000400
#define XPAR=5FOPB=5FINTC=5F0=5FDDR=5FSDRAM=5F32MX64=5FIP2INTC=5FIRPT=5FINTR 10
#define XPAR=5FRS232=5FUART=5FINTERRUPT=5FMASK 0X000800
#define XPAR=5FOPB=5FINTC=5F0=5FRS232=5FUART=5FINTERRUPT=5FINTR 11

/******************************************************************/

/* Definitions for driver DDR */
#define XPAR=5FXDDR=5FNUM=5FINSTANCES 1

/* Definitions for peripheral DDR=5FSDRAM=5F32MX64 */
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FECC=5FBASEADDR 0xFFFFFFFF
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FECC=5FHIGHADDR 0x00000000
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FDEVICE=5FID 0
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FINCLUDE=5FECC=5FINTR 0


/******************************************************************/

/* Definitions for peripheral DDR=5FSDRAM=5F32MX64 */
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FMEM0=5FBASEADDR 0x00000000
#define XPAR=5FDDR=5FSDRAM=5F32MX64=5FMEM0=5FHIGHADDR 0x0FFFFFFF

/******************************************************************/


/* Definitions for peripheral PLB=5FBRAM=5FIF=5FCNTLR=5F1 */
#define XPAR=5FPLB=5FBRAM=5FIF=5FCNTLR=5F1=5FBASEADDR 0xfffe0000
#define XPAR=5FPLB=5FBRAM=5FIF=5FCNTLR=5F1=5FHIGHADDR 0xffffffff


/******************************************************************/

#define XPAR=5FCPU=5FPPC405=5FCORE=5FCLOCK=5FFREQ=5FHZ 100000000

/******************************************************************/

#define XPAR=5FCPU=5FID 0
#define XPAR=5FPPC405=5FID 0
#define XPAR=5FPPC405=5FCORE=5FCLOCK=5FFREQ=5FHZ 100000000
#define XPAR=5FPPC405=5FISOCM=5FDCR=5FBASEADDR 0x00000010
#define XPAR=5FPPC405=5FISOCM=5FDCR=5FHIGHADDR 0x00000013
#define XPAR=5FPPC405=5FDSOCM=5FDCR=5FBASEADDR 0x00000020
#define XPAR=5FPPC405=5FDSOCM=5FDCR=5FHIGHADDR 0x00000023
#define XPAR=5FPPC405=5FDISABLE=5FOPERAND=5FFORWARDING 1
#define XPAR=5FPPC405=5FDETERMINISTIC=5FMULT 0
#define XPAR=5FPPC405=5FMMU=5FENABLE 1
#define XPAR=5FPPC405=5FDCR=5FRESYNC 0
#define XPAR=5FPPC405=5FHW=5FVER "2.00.c"

/******************************************************************/


/******************************************************************/

/* Cannonical Constant Names */

/******************************************************************/

#define XPAR=5FUARTLITE=5F0=5FBASEADDR XPAR=5FRS232=5FUART=5FBASEADDR
#define XPAR=5FUARTLITE=5F0=5FHIGHADDR XPAR=5FRS232=5FUART=5FHIGHADDR
#define XPAR=5FUARTLITE=5F0=5FDEVICE=5FID XPAR=5FRS232=5FUART=5FDEVICE=5FID

/******************************************************************/

#define XPAR=5FSPI=5F0=5FBASEADDR XPAR=5FSPI=5FEEPROM=5FBASEADDR
#define XPAR=5FSPI=5F0=5FHIGHADDR XPAR=5FSPI=5FEEPROM=5FHIGHADDR
#define XPAR=5FSPI=5F0=5FFIFO=5FEXIST XPAR=5FSPI=5FEEPROM=5FFIFO=5FEXIST
#define XPAR=5FSPI=5F0=5FSPI=5FSLAVE=5FONLY XPAR=5FSPI=5FEEPROM=5FSPI=5FSLAVE=5FONLY
#define XPAR=5FSPI=5F0=5FNUM=5FSS=5FBITS XPAR=5FSPI=5FEEPROM=5FNUM=5FSS=5FBITS
#define XPAR=5FSPI=5F0=5FDEVICE=5FID XPAR=5FSPI=5FEEPROM=5FDEVICE=5FID

/******************************************************************/

#define XPAR=5FSYSACE=5F0=5FBASEADDR XPAR=5FSYSACE=5FCOMPACTFLASH=5FBASEADDR
#define XPAR=5FSYSACE=5F0=5FHIGHADDR XPAR=5FSYSACE=5FCOMPACTFLASH=5FHIGHADDR
#define XPAR=5FSYSACE=5F0=5FDEVICE=5FID XPAR=5FSYSACE=5FCOMPACTFLASH=5FDEVICE=5FID

/******************************************************************/

#define XPAR=5FINTC=5F0=5FBASEADDR XPAR=5FOPB=5FINTC=5F0=5FBASEADDR
#define XPAR=5FINTC=5F0=5FHIGHADDR XPAR=5FOPB=5FINTC=5F0=5FHIGHADDR
#define XPAR=5FINTC=5F0=5FKIND=5FOF=5FINTR XPAR=5FOPB=5FINTC=5F0=5FKIND=5FOF=5FINTR
#define XPAR=5FINTC=5F0=5FDEVICE=5FID XPAR=5FOPB=5FINTC=5F0=5FDEVICE=5FID

/******************************************************************/

#define XPAR=5FINTC=5F0=5FSYSACE=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FSYSACE=5FCOMPACTFLASH=5FSY=
SACE=5FIRQ=5FINTR
#define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FA XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR=
PT=5FINTR
#define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FB XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR=
PT=5FINTR
#define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FC XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR=
PT=5FINTR
#define XPAR=5FINTC=5F0=5FPCI=5F0=5FVEC=5FID=5FD XPAR=5FOPB=5FINTC=5F0=5FPCI32=5FBRIDGE=5FIP2INTC=5FIR=
PT=5FINTR
#define XPAR=5FINTC=5F0=5FSPI=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FSPI=5FEEPROM=5FIP2INTC=5FIRPT=5FI=
NTR
#define XPAR=5FINTC=5F0=5FDDR=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FDDR=5FSDRAM=5F32MX64=5FIP2INTC=5F=
IRPT=5FINTR
#define XPAR=5FINTC=5F0=5FUARTLITE=5F0=5FVEC=5FID XPAR=5FOPB=5FINTC=5F0=5FRS232=5FUART=5FINTERRUPT=
=5FINTR

/******************************************************************/

#define XPAR=5FPLB=5FCLOCK=5FFREQ=5FHZ 100000000
#define XPAR=5FCORE=5FCLOCK=5FFREQ=5FHZ XPAR=5FCPU=5FPPC405=5FCORE=5FCLOCK=5FFREQ=5FHZ
#define XPAR=5FDDR=5F0=5FSIZE 0x10000000

/******************************************************************/

#define XPAR=5FPCI=5F0=5FCLOCK=5FFREQ=5FHZ    0

/******************************************************************/

=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F=5F
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On 1/10/08, Joachim Meyer [off-list ref] wrote:

Hi again

I tried my compiled kernel this morning.
I loaded my Bitstream onto the FPGA, then the zImage.elf via xmd: dow zIm=

age.elf.

After I typed "run" I got foolowing message on an Terminal:
------------------------------------------------------------------------
loaded at:     00400000 004F219C
board data at: 004F0120 004F019C
relocated to:  00404048 004040C4
zimage at:     00404E39 004EF931
avail ram:     004F3000 10000000

Linux/PPC load: console=3DttyS0,9600

                          ^^^^^^^^^^
should be 'console=3DttyUL0'

Uncompressing Linux...done.
Now booting the kernel

------------------------------------------------------------------------
Doesn't look that bad I think. ;)
The Question I have is of course why he stops there.
Is it why He can't find a rootfs?
Or would he say this in that case.
I found someone with an similar Problem:
http://lists.ppckernel.org/pipermail/ppckernel/2006-May/000026.html
but I already use the xparameters_ml310 from my BSP.
Where must I look for the error?
There where some warnings when I compiled the kernel. Is this ok?

Greets & THX
Joachim

PS: My xparameters_ml310.h
-------------------------------------------------------------------------=

-----------------------------------------------

/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 9.1.02 EDK_J_SP2.4
* DO NOT EDIT.
*
* Copyright (c) 2005 Xilinx, Inc.  All rights reserved.
*
* Description: Driver parameters
*
*******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral RS232_UART */
#define XPAR_RS232_UART_BASEADDR 0x40600000
#define XPAR_RS232_UART_HIGHADDR 0x4060FFFF
#define XPAR_RS232_UART_DEVICE_ID 0
#define XPAR_RS232_UART_BAUDRATE 9600
#define XPAR_RS232_UART_USE_PARITY 0
#define XPAR_RS232_UART_ODD_PARITY 0
#define XPAR_RS232_UART_DATA_BITS 8


/******************************************************************/

/* Definitions for driver SPI */
#define XPAR_XSPI_NUM_INSTANCES 1

/* Definitions for peripheral SPI_EEPROM */
#define XPAR_SPI_EEPROM_BASEADDR 0x4B308000
#define XPAR_SPI_EEPROM_HIGHADDR 0x4B30807F
#define XPAR_SPI_EEPROM_DEVICE_ID 0
#define XPAR_SPI_EEPROM_FIFO_EXIST 1
#define XPAR_SPI_EEPROM_SPI_SLAVE_ONLY 0
#define XPAR_SPI_EEPROM_NUM_SS_BITS 1


/******************************************************************/

/* Definitions for driver PCI */
#define XPAR_XPCI_NUM_INSTANCES 1

/* Definitions for peripheral PCI32_BRIDGE */
#define XPAR_PCI32_BRIDGE_DEVICE_ID 0
#define XPAR_PCI32_BRIDGE_BASEADDR 0x42600000
#define XPAR_PCI32_BRIDGE_HIGHADDR 0x4260FFFF
#define XPAR_PCI32_BRIDGE_PCIBAR_0 0x00000000
#define XPAR_PCI32_BRIDGE_PCIBAR_LEN_0 7
#define XPAR_PCI32_BRIDGE_PCIBAR2IPIF_0 0
#define XPAR_PCI32_BRIDGE_PCIBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_PCI32_BRIDGE_PCI_PREFETCH_0 1
#define XPAR_PCI32_BRIDGE_PCI_SPACETYPE_0 1
#define XPAR_PCI32_BRIDGE_PCIBAR_1 0xffffffff
#define XPAR_PCI32_BRIDGE_PCIBAR_LEN_1 20
#define XPAR_PCI32_BRIDGE_PCIBAR2IPIF_1 0
#define XPAR_PCI32_BRIDGE_PCIBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_PCI32_BRIDGE_PCI_PREFETCH_1 1
#define XPAR_PCI32_BRIDGE_PCI_SPACETYPE_1 1
#define XPAR_PCI32_BRIDGE_PCIBAR_2 0xffffffff
#define XPAR_PCI32_BRIDGE_PCIBAR_LEN_2 20
#define XPAR_PCI32_BRIDGE_PCIBAR2IPIF_2 0
#define XPAR_PCI32_BRIDGE_PCIBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_PCI32_BRIDGE_PCI_PREFETCH_2 1
#define XPAR_PCI32_BRIDGE_PCI_SPACETYPE_2 1
#define XPAR_PCI32_BRIDGE_IPIFBAR_0 0x60000000
#define XPAR_PCI32_BRIDGE_IPIF_HIGHADDR_0 0x7fffffff
#define XPAR_PCI32_BRIDGE_IPIFBAR2PCI_0 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_PCI32_BRIDGE_IPIF_PREFETCH_0 1
#define XPAR_PCI32_BRIDGE_IPIF_SPACETYPE_0 1
#define XPAR_PCI32_BRIDGE_IPIFBAR_1 0x54000000
#define XPAR_PCI32_BRIDGE_IPIF_HIGHADDR_1 0x57ffffff
#define XPAR_PCI32_BRIDGE_IPIFBAR2PCI_1 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_PCI32_BRIDGE_IPIF_PREFETCH_1 1
#define XPAR_PCI32_BRIDGE_IPIF_SPACETYPE_1 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_2 0xffffffff
#define XPAR_PCI32_BRIDGE_IPIF_HIGHADDR_2 0x00000000
#define XPAR_PCI32_BRIDGE_IPIFBAR2PCI_2 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_PCI32_BRIDGE_IPIF_PREFETCH_2 1
#define XPAR_PCI32_BRIDGE_IPIF_SPACETYPE_2 1
#define XPAR_PCI32_BRIDGE_IPIFBAR_3 0xffffffff
#define XPAR_PCI32_BRIDGE_IPIF_HIGHADDR_3 0x00000000
#define XPAR_PCI32_BRIDGE_IPIFBAR2PCI_3 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
#define XPAR_PCI32_BRIDGE_IPIF_PREFETCH_3 1
#define XPAR_PCI32_BRIDGE_IPIF_SPACETYPE_3 1
#define XPAR_PCI32_BRIDGE_IPIFBAR_4 0xffffffff
#define XPAR_PCI32_BRIDGE_IPIF_HIGHADDR_4 0x00000000
#define XPAR_PCI32_BRIDGE_IPIFBAR2PCI_4 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
#define XPAR_PCI32_BRIDGE_IPIF_PREFETCH_4 1
#define XPAR_PCI32_BRIDGE_IPIF_SPACETYPE_4 1
#define XPAR_PCI32_BRIDGE_IPIFBAR_5 0xffffffff
#define XPAR_PCI32_BRIDGE_IPIF_HIGHADDR_5 0x00000000
#define XPAR_PCI32_BRIDGE_IPIFBAR2PCI_5 0
#define XPAR_PCI32_BRIDGE_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
#define XPAR_PCI32_BRIDGE_IPIF_PREFETCH_5 1
#define XPAR_PCI32_BRIDGE_IPIF_SPACETYPE_5 1
#define XPAR_PCI32_BRIDGE_DMA_BASEADDR 0xFFFFFFFF
#define XPAR_PCI32_BRIDGE_DMA_HIGHADDR 0x00000000
#define XPAR_PCI32_BRIDGE_DMA_CHAN_TYPE 9
#define XPAR_PCI32_BRIDGE_DMA_LENGTH_WIDTH 13
#define XPAR_PCI32_BRIDGE_BRIDGE_IDSEL_ADDR_BIT 16


/******************************************************************/

#define XPAR_XSYSACE_MEM_WIDTH 8
/* Definitions for driver SYSACE */
#define XPAR_XSYSACE_NUM_INSTANCES 1

/* Definitions for peripheral SYSACE_COMPACTFLASH */
#define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000
#define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF
#define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0
#define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 8


/******************************************************************/

#define XPAR_INTC_MAX_NUM_INTR_INPUTS 12
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral OPB_INTC_0 */
#define XPAR_OPB_INTC_0_BASEADDR 0x41200000
#define XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_OPB_INTC_0_DEVICE_ID 0
#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000C00


/******************************************************************/

#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_SBR_INT_MASK 0X000001
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_SBR_INT_INTR 0
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTF_MASK 0X000002
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTF_INTR 1
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTE_MASK 0X000004
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTE_INTR 2
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTD_MASK 0X000008
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTD_INTR 3
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTC_MASK 0X000010
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTC_INTR 4
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTB_MASK 0X000020
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTB_INTR 5
#define XPAR_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTA_MASK 0X000040
#define XPAR_OPB_INTC_0_SYSTEM_FPGA_0_PCI32_BRIDGE_PCI_INTA_INTR 6
#define XPAR_SYSACE_COMPACTFLASH_SYSACE_IRQ_MASK 0X000080
#define XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR 7
#define XPAR_PCI32_BRIDGE_IP2INTC_IRPT_MASK 0X000100
#define XPAR_OPB_INTC_0_PCI32_BRIDGE_IP2INTC_IRPT_INTR 8
#define XPAR_SPI_EEPROM_IP2INTC_IRPT_MASK 0X000200
#define XPAR_OPB_INTC_0_SPI_EEPROM_IP2INTC_IRPT_INTR 9
#define XPAR_DDR_SDRAM_32MX64_IP2INTC_IRPT_MASK 0X000400
#define XPAR_OPB_INTC_0_DDR_SDRAM_32MX64_IP2INTC_IRPT_INTR 10
#define XPAR_RS232_UART_INTERRUPT_MASK 0X000800
#define XPAR_OPB_INTC_0_RS232_UART_INTERRUPT_INTR 11

/******************************************************************/

/* Definitions for driver DDR */
#define XPAR_XDDR_NUM_INSTANCES 1

/* Definitions for peripheral DDR_SDRAM_32MX64 */
#define XPAR_DDR_SDRAM_32MX64_ECC_BASEADDR 0xFFFFFFFF
#define XPAR_DDR_SDRAM_32MX64_ECC_HIGHADDR 0x00000000
#define XPAR_DDR_SDRAM_32MX64_DEVICE_ID 0
#define XPAR_DDR_SDRAM_32MX64_INCLUDE_ECC_INTR 0


/******************************************************************/

/* Definitions for peripheral DDR_SDRAM_32MX64 */
#define XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR 0x00000000
#define XPAR_DDR_SDRAM_32MX64_MEM0_HIGHADDR 0x0FFFFFFF

/******************************************************************/


/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */
#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xfffe0000
#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff


/******************************************************************/

#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000

/******************************************************************/

#define XPAR_CPU_ID 0
#define XPAR_PPC405_ID 0
#define XPAR_PPC405_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_PPC405_ISOCM_DCR_BASEADDR 0x00000010
#define XPAR_PPC405_ISOCM_DCR_HIGHADDR 0x00000013
#define XPAR_PPC405_DSOCM_DCR_BASEADDR 0x00000020
#define XPAR_PPC405_DSOCM_DCR_HIGHADDR 0x00000023
#define XPAR_PPC405_DISABLE_OPERAND_FORWARDING 1
#define XPAR_PPC405_DETERMINISTIC_MULT 0
#define XPAR_PPC405_MMU_ENABLE 1
#define XPAR_PPC405_DCR_RESYNC 0
#define XPAR_PPC405_HW_VER "2.00.c"

/******************************************************************/


/******************************************************************/

/* Cannonical Constant Names */

/******************************************************************/

#define XPAR_UARTLITE_0_BASEADDR XPAR_RS232_UART_BASEADDR
#define XPAR_UARTLITE_0_HIGHADDR XPAR_RS232_UART_HIGHADDR
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID

/******************************************************************/

#define XPAR_SPI_0_BASEADDR XPAR_SPI_EEPROM_BASEADDR
#define XPAR_SPI_0_HIGHADDR XPAR_SPI_EEPROM_HIGHADDR
#define XPAR_SPI_0_FIFO_EXIST XPAR_SPI_EEPROM_FIFO_EXIST
#define XPAR_SPI_0_SPI_SLAVE_ONLY XPAR_SPI_EEPROM_SPI_SLAVE_ONLY
#define XPAR_SPI_0_NUM_SS_BITS XPAR_SPI_EEPROM_NUM_SS_BITS
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_EEPROM_DEVICE_ID

/******************************************************************/

#define XPAR_SYSACE_0_BASEADDR XPAR_SYSACE_COMPACTFLASH_BASEADDR
#define XPAR_SYSACE_0_HIGHADDR XPAR_SYSACE_COMPACTFLASH_HIGHADDR
#define XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMPACTFLASH_DEVICE_ID

/******************************************************************/

#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID

/******************************************************************/

#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_SYSACE_COMPACTFLASH_S=

YSACE_IRQ_INTR

#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_OPB_INTC_0_PCI32_BRIDGE_IP2INTC_I=

RPT_INTR

#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_OPB_INTC_0_PCI32_BRIDGE_IP2INTC_I=

RPT_INTR

#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_OPB_INTC_0_PCI32_BRIDGE_IP2INTC_I=

RPT_INTR

#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_OPB_INTC_0_PCI32_BRIDGE_IP2INTC_I=

RPT_INTR

#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_OPB_INTC_0_SPI_EEPROM_IP2INTC_IRPT_=

INTR

#define XPAR_INTC_0_DDR_0_VEC_ID XPAR_OPB_INTC_0_DDR_SDRAM_32MX64_IP2INTC=

_IRPT_INTR

#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_OPB_INTC_0_RS232_UART_INTERRUP=

T_INTR

/******************************************************************/

#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
#define XPAR_DDR_0_SIZE 0x10000000

/******************************************************************/

#define XPAR_PCI_0_CLOCK_FREQ_HZ    0

/******************************************************************/

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Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.