Hello!
I'm building a new Virtex4-FX60 device. I have built it with the new
MPMC3 and a 256MB SO-DIMM. It works successfully with a "mem-test" type
embedded program.
I cannot get it to boot a Linux kernel. I have traced it down to the
MMU not getting mapped correctly.
I can load the kernel via jtag, get the pre-boot messages on the serial
but then when it tries to jump to 0xc0002218 (start_here: head_4xxx.S)
it fails with a "Machine check exception; invalid instruction address".
Using the debugger and examining the memory once the mmu is suppose to
be configured, I see that it is not mapping 0xc0000000 to the proper
location. I'm sure I've set something up wrong in my FPGA and I need to
re-synthesize. But what?
Any hints on which registers to look for or what I need to do??
RJW.
On 1/7/08, Robert Woodworth [off-list ref] wrote:
Hello!
I'm building a new Virtex4-FX60 device. I have built it with the new
MPMC3 and a 256MB SO-DIMM. It works successfully with a "mem-test" type
embedded program.
I cannot get it to boot a Linux kernel. I have traced it down to the
MMU not getting mapped correctly.
I can load the kernel via jtag, get the pre-boot messages on the serial
but then when it tries to jump to 0xc0002218 (start_here: head_4xxx.S)
it fails with a "Machine check exception; invalid instruction address".
Using the debugger and examining the memory once the mmu is suppose to
be configured, I see that it is not mapping 0xc0000000 to the proper
location. I'm sure I've set something up wrong in my FPGA and I need to
re-synthesize. But what?
Hmmm, I haven't seen that failure mode before. MMU handling on an of
my virtex platforms has never been a problem. Take a look at the TLB
registers to see how they are configured to see if the mappings are
really getting written.
What kernel version are you using?
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
After further investigation...
There is a pending interrupt from the PLB waiting at bootup and it gets
hit by Linux when the MSR gets set and enables critical interrupts (same
time that it jumps into 0xC000XXXX). The kernel code detects the
interrupt as a PLB data bus error and goes into crash sequence die().
I think I have a problem with my reset hardware, such that the PLB is
not getting reset correctly with the PPC. With all interrupts disabled
and running a standalone C program, the PLB and memory work fine.
Any Virtex experts out there have any hints?
RJW.
On Mon, 2008-01-07 at 11:21 -0700, Grant Likely wrote:
On 1/7/08, Robert Woodworth [off-list ref] wrote:
quoted
Hello!
I'm building a new Virtex4-FX60 device. I have built it with the new
MPMC3 and a 256MB SO-DIMM. It works successfully with a "mem-test" type
embedded program.
I cannot get it to boot a Linux kernel. I have traced it down to the
MMU not getting mapped correctly.
I can load the kernel via jtag, get the pre-boot messages on the serial
but then when it tries to jump to 0xc0002218 (start_here: head_4xxx.S)
it fails with a "Machine check exception; invalid instruction address".
Using the debugger and examining the memory once the mmu is suppose to
be configured, I see that it is not mapping 0xc0000000 to the proper
location. I'm sure I've set something up wrong in my FPGA and I need to
re-synthesize. But what?
Hmmm, I haven't seen that failure mode before. MMU handling on an of
my virtex platforms has never been a problem. Take a look at the TLB
registers to see how they are configured to see if the mappings are
really getting written.
What kernel version are you using?
Cheers,
g.
Passed along....
"Most likely bootloop is not enabled. The processor takes an invalid
instruction and registers a following machine check exception. The
machine check exception is taken when it is enabled in the MSR causing
Linux to crash."
Steve
-----Original Message-----
From: linuxppc-embedded-bounces+stephen=3Dneuendorffer.name@ozlabs.org
[mailto:linuxppc-embedded-
bounces+stephen=3Dneuendorffer.name@ozlabs.org] On Behalf Of Robert
Woodworth
Sent: Tuesday, January 08, 2008 1:55 PM
To: Grant Likely
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: MMU failure, Virtex4-FX60
=20
After further investigation...
There is a pending interrupt from the PLB waiting at bootup and it
gets
hit by Linux when the MSR gets set and enables critical interrupts
(same
time that it jumps into 0xC000XXXX). The kernel code detects the
interrupt as a PLB data bus error and goes into crash sequence die().
=20
I think I have a problem with my reset hardware, such that the PLB is
not getting reset correctly with the PPC. With all interrupts
disabled
and running a standalone C program, the PLB and memory work fine.
Any Virtex experts out there have any hints?
=20
=20
=20
RJW.
=20
=20
=20
=20
On Mon, 2008-01-07 at 11:21 -0700, Grant Likely wrote:
quoted
On 1/7/08, Robert Woodworth [off-list ref] wrote:
quoted
Hello!
I'm building a new Virtex4-FX60 device. I have built it with the
new
quoted
quoted
MPMC3 and a 256MB SO-DIMM. It works successfully with a
"mem-test" type
quoted
quoted
embedded program.
I cannot get it to boot a Linux kernel. I have traced it down to
the
quoted
quoted
MMU not getting mapped correctly.
I can load the kernel via jtag, get the pre-boot messages on the
serial
quoted
quoted
but then when it tries to jump to 0xc0002218 (start_here:
head_4xxx.S)
quoted
quoted
it fails with a "Machine check exception; invalid instruction
address".
quoted
quoted
Using the debugger and examining the memory once the mmu is
suppose to
quoted
quoted
be configured, I see that it is not mapping 0xc0000000 to the
proper
quoted
quoted
location. I'm sure I've set something up wrong in my FPGA and I
need to
quoted
quoted
re-synthesize. But what?
Hmmm, I haven't seen that failure mode before. MMU handling on an
of
quoted
my virtex platforms has never been a problem. Take a look at the
TLB
quoted
registers to see how they are configured to see if the mappings are
really getting written.
What kernel version are you using?
Cheers,
g.
=20
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