[PATCH respin 0/7] MPC8568E-MDS related patches

Hello Kumar,

This is respin of MPC8568E-MDS patches, on top of master branch
as of today.

If there are no objections against SPI patch, please Ack it, thus
David could pick it up.

Thanks,

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

Currently, all QE SPI controllers are almost the same comparing to
MPC83xx's, thus let's use that driver for them.

Tested to work on MPC85xx in loopback mode.

Signed-off-by: Anton Vorontsov <redacted>
---

This is respin. Hope this time it will get ack from the
PowerPC team.

 drivers/spi/Kconfig |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b915711..a77ede5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig

@@ -124,16 +124,17 @@ config SPI_MPC52xx_PSC
 	  Controller in master SPI mode.
 
 config SPI_MPC83xx
-	tristate "Freescale MPC83xx SPI controller"
-	depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
+	tristate "Freescale MPC83xx/QUICC Engine SPI controller"
+	depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
 	select SPI_BITBANG
 	help
-	  This enables using the Freescale MPC83xx SPI controller in master
-	  mode.
+	  This enables using the Freescale MPC83xx and QUICC Engine SPI
+	  controllers in master mode.
 
 	  Note, this driver uniquely supports the SPI controller on the MPC83xx
-	  family of PowerPC processors.  The MPC83xx uses a simple set of shift
-	  registers for data (opposed to the CPM based descriptor model).
+	  family of PowerPC processors, plus processors with QUICC Engine
+	  technology. This driver uses a simple set of shift registers for data
+	  (opposed to the CPM based descriptor model).
 
 config SPI_OMAP_UWIRE
 	tristate "OMAP1 MicroWire"

-- 
1.5.0.6

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

Signed-off-by: Anton Vorontsov <redacted>
---
 arch/powerpc/boot/dts/mpc8568mds.dts |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index b4aa5e7..5439437 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts

@@ -410,7 +410,7 @@
 
 	};
 
-	pci@8000 {
+	pci@e0008000 {
 		interrupt-map-mask = <f800 0 0 7>;
 		interrupt-map = <
 			/* IDSEL 0x12 AD18 */

@@ -434,13 +434,13 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <8000 1000>;
+		reg = <e0008000 1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 	};
 
 	/* PCI Express */
-	pcie@a000 {
+	pcie@e000a000 {
 		interrupt-map-mask = <f800 0 0 7>;
 		interrupt-map = <
 

@@ -459,7 +459,7 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <a000 1000>;
+		reg = <e000a000 1000>;
 		compatible = "fsl,mpc8548-pcie";
 		device_type = "pci";
 		pcie@0 {

-- 
1.5.0.6

Apart from that the current code doesn't compile it's also
meaningless with regard to the MPC8568E-MDS' BCSR.

This patch used to reset UCCs properly.

Signed-off-by: Anton Vorontsov <redacted>
---
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |   28 ++++++++++++++++------------
 1 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 57e840a..6913e99 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c

@@ -113,18 +113,22 @@ static void __init mpc85xx_mds_setup_arch(void)
 	}
 
 	if (bcsr_regs) {
-		u8 bcsr_phy;
-
-		/* Reset the Ethernet PHY */
-		bcsr_phy = in_be8(&bcsr_regs[9]);
-		bcsr_phy &= ~0x20;
-		out_be8(&bcsr_regs[9], bcsr_phy);
-
-		udelay(1000);
-
-		bcsr_phy = in_be8(&bcsr_regs[9]);
-		bcsr_phy |= 0x20;
-		out_be8(&bcsr_regs[9], bcsr_phy);
+#define BCSR_UCC1_GETH_EN	(0x1 << 7)
+#define BCSR_UCC2_GETH_EN	(0x1 << 7)
+#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
+#define BCSR_UCC2_MODE_MSK	(0x3 << 0)
+
+		/* Turn off UCC1 & UCC2 */
+		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+
+		/* Mode is RGMII, all bits clear */
+		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+					 BCSR_UCC2_MODE_MSK);
+
+		/* Turn UCC1 & UCC2 on */
+		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 
 		iounmap(bcsr_regs);
 	}

-- 
1.5.0.6

1. UCC1's RX_DV pin is 16, not 15;
2. UCC1's phy is at 0x7, not 0x1. Schematics says 0x7, and recent
   u-boot also using 0x7.
3. Use gianfar's (eTSEC) mdio bus. This is hardware default setup.
4. tx-clock should be CLK16 (GE125, PB31);
5. phy-connection-type is RGMII-ID;

Signed-off-by: Anton Vorontsov <redacted>
---
 arch/powerpc/boot/dts/mpc8568mds.dts |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 6ac134a..b4aa5e7 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts

@@ -104,10 +104,10 @@
 			device_type = "mdio";
 			compatible = "gianfar";
 			reg = <24520 20>;
-			phy0: ethernet-phy@0 {
+			phy0: ethernet-phy@7 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <0>;
+				reg = <7>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {

@@ -242,7 +242,7 @@
 					4  1a  2  0  2  0 	/* RxD7 */
 					4  0b  1  0  2  0 	/* TX_EN */
 					4  18  1  0  2  0 	/* TX_ER */
-					4  0f  2  0  2  0 	/* RX_DV */
+					4  10  2  0  2  0 	/* RX_DV */
 					4  1e  2  0  2  0 	/* RX_ER */
 					4  11  2  0  2  0 	/* RX_CLK */
 					4  13  1  0  2  0 	/* GTX_CLK */

@@ -334,10 +334,10 @@
 			mac-address = [ 00 00 00 00 00 00 ];
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock = <0>;
-			tx-clock = <19>;
-			phy-handle = <&qe_phy0>;
-			phy-connection-type = "gmii";
+			tx-clock = <20>;
 			pio-handle = <&pio1>;
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
 		};
 
 		ucc@3000 {

@@ -356,10 +356,10 @@
 			mac-address = [ 00 00 00 00 00 00 ];
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock = <0>;
-			tx-clock = <14>;
-			phy-handle = <&qe_phy1>;
-			phy-connection-type = "gmii";
+			tx-clock = <20>;
 			pio-handle = <&pio2>;
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
 		};
 
 		mdio@2120 {

@@ -371,10 +371,10 @@
 
 			/* These are the same PHYs as on
 			 * gianfar's MDIO bus */
-			qe_phy0: ethernet-phy@00 {
+			qe_phy0: ethernet-phy@07 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <0>;
+				reg = <7>;
 				device_type = "ethernet-phy";
 			};
 			qe_phy1: ethernet-phy@01 {

-- 
1.5.0.6

8 bytes padding required to match MPC85xx registers layout.

Signed-off-by: Anton Vorontsov <redacted>
Reviewed-by: Kim Phillips <redacted>
---
 arch/powerpc/sysdev/qe_lib/qe_io.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index a114cb0..e53ea4d 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c

@@ -36,6 +36,9 @@ struct port_regs {
 	__be32	cpdir2;		/* Direction register */
 	__be32	cppar1;		/* Pin assignment register */
 	__be32	cppar2;		/* Pin assignment register */
+#ifdef CONFIG_PPC_85xx
+	u8	pad[8];
+#endif
 };
 
 static struct port_regs *par_io = NULL;

-- 
1.5.0.6

set_irq_chained_handler overwrites MPIC's handle_irq function
(handle_fasteoi_irq) thus MPIC never gets eoi event from the
cascaded IRQ. This situation hangs MPIC on MPC8568E.

To solve this problem efficiently, QEIC needs pluggable handlers,
specific to the underlaying interrupt controller.

Patch extends qe_ic_init() function to accept low and high interrupt
handlers. To avoid #ifdefs, stack of interrupt handlers specified in
the header file and functions are marked 'static inline', thus
handlers are compiled-in only if actually used (in the board file).
Another option would be to lookup for parent controller and
automatically detect handlers (will waste text size because of
never used handlers, so this option abolished).

qe_ic_init() also changed in regard to support multiplexed high/low
lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic()
handler implemented appropriately.

Signed-off-by: Anton Vorontsov <redacted>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 arch/powerpc/platforms/83xx/mpc832x_mds.c |    2 +-
 arch/powerpc/platforms/83xx/mpc832x_rdb.c |    2 +-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |    2 +-
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |    2 +-
 arch/powerpc/sysdev/qe_lib/qe_ic.c        |   29 +++---------
 include/asm-powerpc/qe_ic.h               |   68 ++++++++++++++++++++++++++++-
 6 files changed, 78 insertions(+), 27 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index b8d8c91..972fa85 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c

@@ -140,7 +140,7 @@ static void __init mpc832x_sys_init_IRQ(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }

diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 4da0698..fbca336 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c

@@ -151,7 +151,7 @@ void __init mpc832x_rdb_init_IRQ(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }

diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 0b18a75..0f3855c 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c

@@ -147,7 +147,7 @@ static void __init mpc836x_mds_init_IRQ(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 00f4c3a..57e840a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c

@@ -180,7 +180,7 @@ static void __init mpc85xx_mds_pic_init(void)
 	if (!np)
 		return;
 
-	qe_ic_init(np, 0);
+	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 	of_node_put(np);
 #endif				/* CONFIG_QUICC_ENGINE */
 }

diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 9a2d1ed..e1c0fd6 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c

@@ -321,25 +321,9 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
 	return irq_linear_revmap(qe_ic->irqhost, irq);
 }
 
-void qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = desc->handler_data;
-	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-}
-
-void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = desc->handler_data;
-	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-}
-
-void __init qe_ic_init(struct device_node *node, unsigned int flags)
+void __init qe_ic_init(struct device_node *node, unsigned int flags,
+		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+		void (*high_handler)(unsigned int irq, struct irq_desc *desc))
 {
 	struct qe_ic *qe_ic;
 	struct resource res;

@@ -399,11 +383,12 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
 	qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 
 	set_irq_data(qe_ic->virq_low, qe_ic);
-	set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
+	set_irq_chained_handler(qe_ic->virq_low, low_handler);
 
-	if (qe_ic->virq_high != NO_IRQ) {
+	if (qe_ic->virq_high != NO_IRQ &&
+			qe_ic->virq_high != qe_ic->virq_low) {
 		set_irq_data(qe_ic->virq_high, qe_ic);
-		set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
+		set_irq_chained_handler(qe_ic->virq_high, high_handler);
 	}
 }
 

diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
index e386fb7..a779b2c 100644
--- a/include/asm-powerpc/qe_ic.h
+++ b/include/asm-powerpc/qe_ic.h

@@ -56,9 +56,75 @@ enum qe_ic_grp_id {
 	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */
 };
 
-void qe_ic_init(struct device_node *node, unsigned int flags);
+void qe_ic_init(struct device_node *node, unsigned int flags,
+		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+		void (*high_handler)(unsigned int irq, struct irq_desc *desc));
 void qe_ic_set_highest_priority(unsigned int virq, int high);
 int qe_ic_set_priority(unsigned int virq, unsigned int priority);
 int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
 
+struct qe_ic;
+unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
+unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
+
+static inline void qe_ic_cascade_low_ipic(unsigned int irq,
+					  struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_high_ipic(unsigned int irq,
+					   struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_low_mpic(unsigned int irq,
+					  struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_high_mpic(unsigned int irq,
+					   struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
+					    struct irq_desc *desc)
+{
+	struct qe_ic *qe_ic = desc->handler_data;
+	unsigned int cascade_irq;
+
+	cascade_irq = qe_ic_get_high_irq(qe_ic);
+	if (cascade_irq == NO_IRQ)
+		cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+	if (cascade_irq != NO_IRQ)
+		generic_handle_irq(cascade_irq);
+
+	desc->chip->eoi(irq);
+}
+
 #endif /* _ASM_POWERPC_QE_IC_H */

-- 
1.5.0.6

Signed-off-by: Anton Vorontsov <redacted>
---
 arch/powerpc/platforms/85xx/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index b8476b2..cf815b2 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig

@@ -25,7 +25,7 @@ config MPC85xx_CDS
 config MPC85xx_MDS
 	bool "Freescale MPC85xx MDS"
 	select DEFAULT_UIMAGE
-#	select QUICC_ENGINE
+	select QUICC_ENGINE
 	help
 	  This option enables support for the MPC85xx MDS board
 

-- 
1.5.0.6

Hello.

Anton Vorontsov wrote:

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

    Of course. But shouldn't those be the subnoses of the "soc" type node?
I don't suppose the PCI controllers could hang off the root node... :-/

Signed-off-by: Anton Vorontsov <redacted>

WBR, Sergei

On Fri, Oct 05, 2007 at 09:56:46PM +0400, Sergei Shtylyov wrote:

Hello.

Anton Vorontsov wrote:

quoted

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

    Of course. But shouldn't those be the subnoses of the "soc" type node?

No -- the soc node is for immr/ccsr only, and while the PCI control
registers are there, the ranges are not.  There was a lengthy discussion on
IRC about this a couple weeks ago.  It'd be cleaner to split the control
node from the bus node, and connect them with phandles, but some people
didn't like that, and this is what we compromised on.

-Scott

On Fri, Oct 05, 2007 at 09:56:46PM +0400, Sergei Shtylyov wrote:

Hello.

Anton Vorontsov wrote:

quoted

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

   Of course. But shouldn't those be the subnoses of the "soc" type node?

Nope. PCI's ranges = <>; isn't in the SOC address space.

Valentine Barshak posted a patch titled "[RFC] [PATCH] PowerPC: Add 64-bit
phys addr support to 32-bit pci" that started using of_translate_address()
for ranges, and of_translate_address() will not work if PCI placed in the
SOC node. Not sure if that patch applied or not, though.

Good luck,

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

On Oct 5, 2007, at 1:05 PM, Anton Vorontsov wrote:

On Fri, Oct 05, 2007 at 09:56:46PM +0400, Sergei Shtylyov wrote:

quoted

Hello.

Anton Vorontsov wrote:

quoted

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

   Of course. But shouldn't those be the subnoses of the "soc"  
type node?

Nope. PCI's ranges = <>; isn't in the SOC address space.

Valentine Barshak posted a patch titled "[RFC] [PATCH] PowerPC: Add  
64-bit
phys addr support to 32-bit pci" that started using  
of_translate_address()
for ranges, and of_translate_address() will not work if PCI placed  
in the
SOC node. Not sure if that patch applied or not, though.

I'm confused, what's the actual issue with PCI that this patch  
addresses?

- k

On Oct 5, 2007, at 12:40 PM, Anton Vorontsov wrote:

Hello Kumar,

This is respin of MPC8568E-MDS patches, on top of master branch
as of today.

If there are no objections against SPI patch, please Ack it, thus
David could pick it up.

I've applied patches 1-5 however I'm not able to get UCC enet working  
on my board.  Is there something special that has to be done?  (I've  
got the card standalone, no MDS backplane).

I'm using the 1.3.0-rc2 u-boot w/o any modifications.

Also, I tried a PCIe e1000 card w/the .dts that's in my tree and that  
works w/o any issue.

- k

Hello Kumar,

On Fri, 5 Oct 2007 15:58:00 -0500
Kumar Gala wrote:

=20
On Oct 5, 2007, at 1:05 PM, Anton Vorontsov wrote:
=20

quoted

On Fri, Oct 05, 2007 at 09:56:46PM +0400, Sergei Shtylyov wrote:

quoted

Hello.

Anton Vorontsov wrote:

quoted

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

   Of course. But shouldn't those be the subnoses of the "soc" =20
type node?

Nope. PCI's ranges =3D <>; isn't in the SOC address space.

Valentine Barshak posted a patch titled "[RFC] [PATCH] PowerPC: Add =20
64-bit
phys addr support to 32-bit pci" that started using =20
of_translate_address()
for ranges, and of_translate_address() will not work if PCI placed =20
in the
SOC node. Not sure if that patch applied or not, though.

=20
I'm confused, what's the actual issue with PCI that this patch =20
addresses?
=20

=46rom what I can see, move of the PCI node out of the SoC node, inspired by =
the recent flame talk about it :)
I guess pretty soon, we'll have "proper" ranges parsing for pci, that does =
of_translate_address() and requires
either tuned-up parent ranges, or residing outside of the SoC node, this is=
 the reason...

- k
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev

--=20
Sincerely, Vitaly

On Fri, Oct 05, 2007 at 03:58:00PM -0500, Kumar Gala wrote:

On Oct 5, 2007, at 1:05 PM, Anton Vorontsov wrote:

quoted

On Fri, Oct 05, 2007 at 09:56:46PM +0400, Sergei Shtylyov wrote:

quoted

Hello.

Anton Vorontsov wrote:

quoted

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

   Of course. But shouldn't those be the subnoses of the "soc" type node?

Nope. PCI's ranges = <>; isn't in the SOC address space.

Valentine Barshak posted a patch titled "[RFC] [PATCH] PowerPC: Add 64-bit
phys addr support to 32-bit pci" that started using of_translate_address()
for ranges, and of_translate_address() will not work if PCI placed in the
SOC node. Not sure if that patch applied or not, though.

I'm confused, what's the actual issue with PCI that this patch addresses?

Which patch? Valentine's or mine under the subject? Don't know about the
former, but mine patch is pretty obvious: your commit
5bece127f0666996ca90772229e00332a34e516c moved PCI nodes out of soc node,
but you forgot to change regs = <>, thus instead of e000a000/e0008000,
kernel used a000/8000 for accessing PCI ccsr registers.

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

On Fri, Oct 05, 2007 at 05:09:28PM -0500, Kumar Gala wrote:

On Oct 5, 2007, at 12:40 PM, Anton Vorontsov wrote:

quoted

Hello Kumar,

This is respin of MPC8568E-MDS patches, on top of master branch
as of today.

If there are no objections against SPI patch, please Ack it, thus
David could pick it up.

I've applied patches 1-5 however I'm not able to get UCC enet working on my 
board.

I wonder how you managed to boot it w/o sixth (PCI) patch in this patch set,
for me board hanged w/o it.

Is there something special that has to be done?  (I've got the card 
standalone, no MDS backplane).

Nothing special, from what I can remember. Though, double checking switches
on the board might help.

Also, .config and bootlog would help.

I'm using the 1.3.0-rc2 u-boot w/o any modifications.

1.2.0-g60174746 here.

Also, I tried a PCIe e1000 card w/the .dts that's in my tree and that works 
w/o any issue.

Strange enough. I'd say it's impossible with your current tree. Maybe you've
used some stale dtb? Because dts is seriously broken as now, and I can't
believe that it worked for you. ;-)

Thanks,

-- 
Anton Vorontsov
email: cbou@mail.ru
backup email: ya-cbou@yandex.ru
irc://irc.freenode.net/bd2

On Oct 8, 2007, at 7:08 AM, Anton Vorontsov wrote:

On Fri, Oct 05, 2007 at 03:58:00PM -0500, Kumar Gala wrote:

quoted

On Oct 5, 2007, at 1:05 PM, Anton Vorontsov wrote:

quoted

On Fri, Oct 05, 2007 at 09:56:46PM +0400, Sergei Shtylyov wrote:

quoted

Hello.

Anton Vorontsov wrote:

quoted

Commit 5bece127f0666996ca90772229e00332a34e516c tried to fix
PCI/PCIe nodes, but actually it broke them even harder. ;-)

   Of course. But shouldn't those be the subnoses of the "soc"  
type node?

Nope. PCI's ranges = <>; isn't in the SOC address space.

Valentine Barshak posted a patch titled "[RFC] [PATCH] PowerPC:  
Add 64-bit
phys addr support to 32-bit pci" that started using  
of_translate_address()
for ranges, and of_translate_address() will not work if PCI  
placed in the
SOC node. Not sure if that patch applied or not, though.

I'm confused, what's the actual issue with PCI that this patch  
addresses?

Which patch? Valentine's or mine under the subject? Don't know  
about the
former, but mine patch is pretty obvious: your commit
5bece127f0666996ca90772229e00332a34e516c moved PCI nodes out of soc  
node,
but you forgot to change regs = <>, thus instead of e000a000/e0008000,
kernel used a000/8000 for accessing PCI ccsr registers.

Yeah, I see that bug now.  It looks like I wasn't getting my new .dts  
on the board.  Will fixup that issue in my patch.

- k

On Oct 8, 2007, at 7:16 AM, Anton Vorontsov wrote:

On Fri, Oct 05, 2007 at 05:09:28PM -0500, Kumar Gala wrote:

quoted

On Oct 5, 2007, at 12:40 PM, Anton Vorontsov wrote:

quoted

Hello Kumar,

This is respin of MPC8568E-MDS patches, on top of master branch
as of today.

If there are no objections against SPI patch, please Ack it, thus
David could pick it up.

I've applied patches 1-5 however I'm not able to get UCC enet  
working on my
board.

I wonder how you managed to boot it w/o sixth (PCI) patch in this  
patch set,
for me board hanged w/o it.

quoted

Is there something special that has to be done?  (I've got the card
standalone, no MDS backplane).

Nothing special, from what I can remember. Though, double checking  
switches
on the board might help.

Also, .config and bootlog would help.

quoted

I'm using the 1.3.0-rc2 u-boot w/o any modifications.

1.2.0-g60174746 here.

quoted

Also, I tried a PCIe e1000 card w/the .dts that's in my tree and  
that works
w/o any issue.

Strange enough. I'd say it's impossible with your current tree.  
Maybe you've
used some stale dtb? Because dts is seriously broken as now, and I  
can't
believe that it worked for you. ;-)

Ignore me. Using the updated dtb makes things work.  I need to double  
check PCIe but UCC geth appears to function now.

- k

quoted

Which patch? Valentine's or mine under the subject? Don't know
about the
former, but mine patch is pretty obvious: your commit
5bece127f0666996ca90772229e00332a34e516c moved PCI nodes out of soc
node,
but you forgot to change regs = <>, thus instead of e000a000/ 
e0008000,
kernel used a000/8000 for accessing PCI ccsr registers.

Yeah, I see that bug now.  It looks like I wasn't getting my new .dts
on the board.  Will fixup that issue in my patch.

Ok, I've tested my updated tree and it works for PCIe with the fix to  
the .dts

- k