RE: Re: PCI target implementation on AMCC PPC CPUs

Hi:

You want to say  PPC440GP cannot be PCI slave without this =
non-transparent bridge because as David said its "interrupt pin register =
hardwired to zero" or there other reasons?=20
I'm trying to use PPC440ep(or epx) and from its datasheet I don't see =
anything about this zero hardwiring. Does it mean "vanilla" PPC440ep =
will work?

And what did you use for PCI Host?

Also, is your code available somwhere?

Thanks,

Leonid.
-----Original Message-----
From: sdeven.lee [mailto:sdeven.lee@163.com]=20
Sent: Thursday, September 06, 2007 7:04 PM
To: David Hawkins
Cc: Leonid; linuxppc-embedded
Subject: Re: Re: PCI target implementation on AMCC PPC CPUs

David Hawkins,=C4=FA=BA=C3=A3=A1

	I have been finished an application using AMCC PPC440GP as PCI =
target(slave) in the last 2 month.I use a non-transparent bridge(AMCC =
PCI6466) to make the device a target(slave) like david has said.

=3D=3D=3D=3D=3D=3D=3D 2007-09-07 04:26:01 =
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Hi Leonid,

In case they are not in the document:

There are several fundamental problems with the AMCC 440EP acting as a=20
PCI target/slave;

1. As a PCI target, there is only one way to generate
   an interrupt to a host; you basically toggle the
   interrupt pin. This makes it tricky to develop a
   host-to-slave communications protocol, eg. its
   hard to use the single interrupt to indicate various
   interrupt states, eg. target-to-host buffer has
   data versus host-to-target buffer has been emptied.
   Ideally AMCC should have implemented mailboxes and/or
   doorbell registers like any other sane PCI target
   device (eg. some the Freescale processors, or any of
   the PLX technologies chips).

2. Look in the data sheet and see if you can figure out
   how the host processor can generate an interrupt to
   the PowerPC core ... oops, you can't. That kind of
   makes it difficult to work with doesn't it.

   A work around would be to have the host write to the
   GPIO register and wire a GPIO pin back to an external
   interrupt pin. Then you would not be able to use any
   other GPIO pin in that GPIO register since there is
   no way to arbitrate host access versus PowerPC core
   access.

This was the other reason I ditched the AMCC part in favor of the=20
Freescale part.

If you are looking at other parts, make sure you look in the PCI=20
configuration space of the processor reference manual. Many processors=20
have the interrupt pin register hardwired to zero, i.e., they can not=20
be used as target devices, only hosts. In that case you'd have to add=20
an intel 21555 non-transparent bridge to make the device a target.

Cheers,
Dave

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=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A1=A12007-09-07

Hi guys,

You want to say  PPC440GP cannot be PCI slave without
this non-transparent bridge because as David said
its "interrupt pin register hardwired to zero" or
there other reasons?  I'm trying to use
PPC440ep(or epx) and from its datasheet I don't
see anything about this zero hardwiring.
Does it mean "vanilla" PPC440ep will work?

Look in the user manual p562

https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440GP/PPC440GP_UM2002_v1_11.pdf

The processor can generate INTA#.

I have been finished an application using AMCC
PPC440GP as PCI target(slave) in the last 2 month.
I use a non-transparent bridge(AMCC PCI6466) to
make the device a target(slave) like david has said.

However in this case, the bridge was not required
to make the processor target-capable. Most likely
the board required a local PCI bus, and so the
non-transparent bridge is used to hide the board
PCI devices from the other PCI host.

In this type of design the processor is acting
a *host* on the target board. When a host wants
to interrupt the target, it asserts an interrupt
in the bridge, and that interrupt asserts an
interrupt input on the processor.

When the target processor wants to interrupt the
host it writes to a register in the bridge and
the bridge interrupt the host using its INTA#.

In both cases the bridge is the target and the
processors are both hosts.

:)

Dave