[PATCH 0/3][POWERPC] Add PCI support for 44xEPx

@@ -478,3 +478,162 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
 	*start = rsrc->start - offset;
 	*end = rsrc->end - offset;
 }
+
+void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
+					    struct device_node *dev, int prim)
+{
+	static unsigned int static_lc_ranges[256];
+	const unsigned int *ranges;
+	unsigned int *lc_ranges;
+	unsigned int pci_space;
+	unsigned long size = 0;
+	int rlen = 0;
+	int orig_rlen, ranges_amnt, i;
+	int memno = 0;
+	struct resource *res;
+	int np, na = of_n_addr_cells(dev);
+	struct ranges_pci64_sz64 *ranges64 = NULL;
+	struct ranges_pci32_sz64 *ranges32 = NULL;
+	phys_addr_t pci_addr, cpu_phys_addr;
+
+	np = na + 5;
+
+	/* From "PCI Binding to 1275"
+	 * The ranges property is laid out as an array of elements,
+	 * each of which comprises:
+	 *   cells 0 - 2:       a PCI address
+	 *   cells 3 or 3+4:    a CPU physical address
+	 *                      (size depending on dev->n_addr_cells)
+	 *   cells 4+5 or 5+6:  the size of the range
+	 */
+	ranges = of_get_property(dev, "ranges", &rlen);
+	if (ranges == NULL)
+		return;
+	/* Sanity check, though hopefully that never happens */
+	if (rlen > sizeof(static_lc_ranges)) {
+		printk(KERN_WARNING "OF ranges property too large !\n");
+		rlen = sizeof(static_lc_ranges);
+	}
+
+	/* Let's work on a copy of the "ranges" property instead
+	 * of damaging the device-tree image in memory
+	 */
+	lc_ranges = static_lc_ranges;
+	memcpy(lc_ranges, ranges, rlen);
+	orig_rlen = rlen;
+
+	ranges = lc_ranges;
+	/* Map ranges to struct according to spec. */
+	if (na >= 2) {
+		ranges64 = (void *)ranges;
+		ranges_amnt = rlen / sizeof(*ranges64);
+	} else {
+		ranges32 = (void *)ranges;
+		ranges_amnt = rlen / sizeof(*ranges32);
+	}
+
+	hose->io_base_phys = 0;
+	for (i = 0; i < ranges_amnt; i++) {
+		res = NULL;
+		if (ranges64) {
+			if (ranges64[i].pci_space == 0)
+				continue;
+
+			pci_space = ranges64[i].pci_space;
+			pci_addr =
+			    (u64) ranges64[i].pci_addr[0] << 32 | ranges64[i].
+			    pci_addr[1];
+			cpu_phys_addr =
+			    of_translate_address(dev, ranges64[i].phys_addr);
+			/*
+			 * I haven't observed 2 significant size cells in kernel
+			 * code, so we're accounting only LSB of size part
+			 * from ranges. -vitb
+			 */
+			size = ranges64[i].size[1];
+#ifdef CONFIG_PPC64
+			if (ranges64[i].size[0])
+				size |= ranges64[i].size[0]<<32;
+#endif
+			DBG("Observed: pci %llx phys %llx size %x\n", pci_addr,
+			    cpu_phys_addr, size);
+		} else {
+			if (ranges32[i].pci_space == 0)
+				continue;
+
+			pci_space = (unsigned int)ranges32[i].pci_space;
+			pci_addr = (unsigned int)ranges32[i].pci_addr[1];
+			cpu_phys_addr = (unsigned int)ranges32[i].phys_addr[0];
+			size = ranges32[i].size[1];
+
+			DBG("Observed: pci %x phys %x size %x\n",
+			    (u32) pci_addr, (u32) cpu_phys_addr, size);
+		}
+
+		switch ((pci_space >> 24) & 0x3) {
+		case 1:	/* I/O space */
+#ifdef CONFIG_PPC32
+			/*
+			 * check from ppc32 pci implementation.
+			 * not sure if it is needed. -vitb
+			 */
+			if (pci_addr != 0)
+				break;
+#endif
+			/* limit I/O space to 16MB */
+			if (size > 0x01000000)
+				size = 0x01000000;
+
+			hose->io_base_phys = cpu_phys_addr - pci_addr;
+			/* handle from 0 to top of I/O window */
+#ifdef CONFIG_PPC64
+			hose->pci_io_size = pci_addr + size;
+#endif
+			hose->io_base_virt = ioremap(hose->io_base_phys, size);
+
+			if (prim)
+				isa_io_base = (unsigned long)hose->io_base_virt;
+
+			res = &hose->io_resource;
+			res->flags = IORESOURCE_IO;
+			res->start = pci_addr;
+			DBG("phb%d: IO 0x%llx -> 0x%llx\n", hose->global_number,
+			    (u64) res->start, (u64) (res->start + size - 1));
+			DBG("IO phys %llx IO virt %p\n",
+			    (u64) hose->io_base_phys, hose->io_base_virt);
+			break;
+		case 2:	/* memory space */
+			memno = 0;
+#ifdef CONFIG_PPC32
+			if ((pci_addr == 0) && (size <= (16 << 20))) {
+				/* 1st 16MB, i.e. ISA memory area */
+				if (prim)
+					isa_mem_base = cpu_phys_addr;
+				memno = 1;
+			}
+#endif
+			while (memno < 3 && hose->mem_resources[memno].flags)
+				++memno;
+
+			if (memno == 0)
+				hose->pci_mem_offset = cpu_phys_addr - pci_addr;
+			if (memno < 3) {
+				res = &hose->mem_resources[memno];
+				res->flags = IORESOURCE_MEM;
+				res->start = cpu_phys_addr;
+				DBG("phb%d: MEM 0x%llx -> 0x%llx\n",
+				    hose->global_number, res->start,
+				    res->start + size - 1);
+			}
+			break;
+		}
+		if (res != NULL) {
+			res->name = dev->full_name;
+			res->end = res->start + size - 1;
+			res->parent = NULL;
+			res->sibling = NULL;
+			res->child = NULL;
+		}
+	}
+}
+

@@ -843,120 +843,6 @@ pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn)
 }
 EXPORT_SYMBOL(pci_device_from_OF_node);
 
-void __init
-pci_process_bridge_OF_ranges(struct pci_controller *hose,
-			   struct device_node *dev, int primary)
-{
-	static unsigned int static_lc_ranges[256] __initdata;
-	const unsigned int *dt_ranges;
-	unsigned int *lc_ranges, *ranges, *prev, size;
-	int rlen = 0, orig_rlen;
-	int memno = 0;
-	struct resource *res;
-	int np, na = of_n_addr_cells(dev);
-	np = na + 5;
-
-	/* First we try to merge ranges to fix a problem with some pmacs
-	 * that can have more than 3 ranges, fortunately using contiguous
-	 * addresses -- BenH
-	 */
-	dt_ranges = of_get_property(dev, "ranges", &rlen);
-	if (!dt_ranges)
-		return;
-	/* Sanity check, though hopefully that never happens */
-	if (rlen > sizeof(static_lc_ranges)) {
-		printk(KERN_WARNING "OF ranges property too large !\n");
-		rlen = sizeof(static_lc_ranges);
-	}
-	lc_ranges = static_lc_ranges;
-	memcpy(lc_ranges, dt_ranges, rlen);
-	orig_rlen = rlen;
-
-	/* Let's work on a copy of the "ranges" property instead of damaging
-	 * the device-tree image in memory
-	 */
-	ranges = lc_ranges;
-	prev = NULL;
-	while ((rlen -= np * sizeof(unsigned int)) >= 0) {
-		if (prev) {
-			if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
-				(prev[2] + prev[na+4]) == ranges[2] &&
-				(prev[na+2] + prev[na+4]) == ranges[na+2]) {
-				prev[na+4] += ranges[na+4];
-				ranges[0] = 0;
-				ranges += np;
-				continue;
-			}
-		}
-		prev = ranges;
-		ranges += np;
-	}
-
-	/*
-	 * The ranges property is laid out as an array of elements,
-	 * each of which comprises:
-	 *   cells 0 - 2:	a PCI address
-	 *   cells 3 or 3+4:	a CPU physical address
-	 *			(size depending on dev->n_addr_cells)
-	 *   cells 4+5 or 5+6:	the size of the range
-	 */
-	ranges = lc_ranges;
-	rlen = orig_rlen;
-	while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
-		res = NULL;
-		size = ranges[na+4];
-		switch ((ranges[0] >> 24) & 0x3) {
-		case 1:		/* I/O space */
-			if (ranges[2] != 0)
-				break;
-			hose->io_base_phys = ranges[na+2];
-			/* limit I/O space to 16MB */
-			if (size > 0x01000000)
-				size = 0x01000000;
-			hose->io_base_virt = ioremap(ranges[na+2], size);
-			if (primary)
-				isa_io_base = (unsigned long) hose->io_base_virt;
-			res = &hose->io_resource;
-			res->flags = IORESOURCE_IO;
-			res->start = ranges[2];
-			DBG("PCI: IO 0x%llx -> 0x%llx\n",
-			    (u64)res->start, (u64)res->start + size - 1);
-			break;
-		case 2:		/* memory space */
-			memno = 0;
-			if (ranges[1] == 0 && ranges[2] == 0
-			    && ranges[na+4] <= (16 << 20)) {
-				/* 1st 16MB, i.e. ISA memory area */
-				if (primary)
-					isa_mem_base = ranges[na+2];
-				memno = 1;
-			}
-			while (memno < 3 && hose->mem_resources[memno].flags)
-				++memno;
-			if (memno == 0)
-				hose->pci_mem_offset = ranges[na+2] - ranges[2];
-			if (memno < 3) {
-				res = &hose->mem_resources[memno];
-				res->flags = IORESOURCE_MEM;
-				if(ranges[0] & 0x40000000)
-					res->flags |= IORESOURCE_PREFETCH;
-				res->start = ranges[na+2];
-				DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno,
-				    (u64)res->start, (u64)res->start + size - 1);
-			}
-			break;
-		}
-		if (res != NULL) {
-			res->name = dev->full_name;
-			res->end = res->start + size - 1;
-			res->parent = NULL;
-			res->sibling = NULL;
-			res->child = NULL;
-		}
-		ranges += np;
-	}
-}
-
 /* We create the "pci-OF-bus-map" property now so it appears in the
  * /proc device tree
  */

@@ -592,100 +592,6 @@ int pci_proc_domain(struct pci_bus *bus)
 	}
 }
 
-void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
-					    struct device_node *dev, int prim)
-{
-	const unsigned int *ranges;
-	unsigned int pci_space;
-	unsigned long size;
-	int rlen = 0;
-	int memno = 0;
-	struct resource *res;
-	int np, na = of_n_addr_cells(dev);
-	unsigned long pci_addr, cpu_phys_addr;
-
-	np = na + 5;
-
-	/* From "PCI Binding to 1275"
-	 * The ranges property is laid out as an array of elements,
-	 * each of which comprises:
-	 *   cells 0 - 2:	a PCI address
-	 *   cells 3 or 3+4:	a CPU physical address
-	 *			(size depending on dev->n_addr_cells)
-	 *   cells 4+5 or 5+6:	the size of the range
-	 */
-	ranges = of_get_property(dev, "ranges", &rlen);
-	if (ranges == NULL)
-		return;
-	hose->io_base_phys = 0;
-	while ((rlen -= np * sizeof(unsigned int)) >= 0) {
-		res = NULL;
-		pci_space = ranges[0];
-		pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
-		cpu_phys_addr = of_translate_address(dev, &ranges[3]);
-		size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
-		ranges += np;
-		if (size == 0)
-			continue;
-
-		/* Now consume following elements while they are contiguous */
-		while (rlen >= np * sizeof(unsigned int)) {
-			unsigned long addr, phys;
-
-			if (ranges[0] != pci_space)
-				break;
-			addr = ((unsigned long)ranges[1] << 32) | ranges[2];
-			phys = ranges[3];
-			if (na >= 2)
-				phys = (phys << 32) | ranges[4];
-			if (addr != pci_addr + size ||
-			    phys != cpu_phys_addr + size)
-				break;
-
-			size += ((unsigned long)ranges[na+3] << 32)
-				| ranges[na+4];
-			ranges += np;
-			rlen -= np * sizeof(unsigned int);
-		}
-
-		switch ((pci_space >> 24) & 0x3) {
-		case 1:		/* I/O space */
-			hose->io_base_phys = cpu_phys_addr - pci_addr;
-			/* handle from 0 to top of I/O window */
-			hose->pci_io_size = pci_addr + size;
-
-			res = &hose->io_resource;
-			res->flags = IORESOURCE_IO;
-			res->start = pci_addr;
-			DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
-				    res->start, res->start + size - 1);
-			break;
-		case 2:		/* memory space */
-			memno = 0;
-			while (memno < 3 && hose->mem_resources[memno].flags)
-				++memno;
-
-			if (memno == 0)
-				hose->pci_mem_offset = cpu_phys_addr - pci_addr;
-			if (memno < 3) {
-				res = &hose->mem_resources[memno];
-				res->flags = IORESOURCE_MEM;
-				res->start = cpu_phys_addr;
-				DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
-					    res->start, res->start + size - 1);
-			}
-			break;
-		}
-		if (res != NULL) {
-			res->name = dev->full_name;
-			res->end = res->start + size - 1;
-			res->parent = NULL;
-			res->sibling = NULL;
-			res->child = NULL;
-		}
-	}
-}
-
 #ifdef CONFIG_HOTPLUG
 
 int pcibios_unmap_io_space(struct pci_bus *bus)

@@ -15,6 +15,22 @@
 #include <linux/pci.h>
 #include <asm/pci-bridge.h>
 
+/* Address-cells and size-cells 2 */
+struct ranges_pci64_sz64 {
+	unsigned int pci_space;
+	unsigned int pci_addr[2];
+	unsigned int phys_addr[2];
+	unsigned int size[2];
+};
+
+/* Address-cells 1 */
+struct ranges_pci32_sz64 {
+	unsigned int pci_space;
+	unsigned int pci_addr[2];
+	unsigned int phys_addr[1];
+	unsigned int size[2];
+};
+
 extern unsigned long isa_io_base;
 
 extern void pci_setup_phb_io(struct pci_controller *hose, int primary);

@@ -92,6 +92,32 @@
 		#size-cells = <1>;
 		ranges;
 		clock-frequency = <0>; /* Filled in by zImage */
+		
+		pci {
+			/* irqs are routed to irq67, dependless of devsel/PIRQx */
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &UIC2 3 8>;	
+
+			interrupt-parent = <&UIC2>;
+			interrupts = <3 8>;
+	    
+			bus-range = <0 0>;
+	
+			/* 
+			 * mem is at 80000000 set up indirectly
+			 * io is at 0001_e800_0000
+			 */
+			ranges = <02000000 0 80000000 1 80000000 0 10000000
+				01000000 0 00000000 1 e8000000 0 00100000>;
+
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+
+    			reg = <1 eec00000 40 1 ef400000 40>;  /* phb cfg, phb reg */
+			compatible = "ibm, 440epx";
+			device_type = "pci";
+		};
 
 		SDRAM0: sdram {
 			device_type = "memory-controller";

@@ -1,8 +1,36 @@
 #ifndef __POWERPC_PLATFORMS_44X_44X_H
 #define __POWERPC_PLATFORMS_44X_44X_H
+#include <asm/pci-bridge.h>
+
+/* PCI support */
+#define PPC4xx_PCI_CFGA_OFFSET		0
+#define PPC4xx_PCI_CFGD_OFFSET		0x4
+
+#define PPC4xx_PCIL0_PMM0LA		0x000
+#define PPC4xx_PCIL0_PMM0MA		0x004
+#define PPC4xx_PCIL0_PMM0PCILA		0x008
+#define PPC4xx_PCIL0_PMM0PCIHA		0x00C
+#define PPC4xx_PCIL0_PMM1LA		0x010
+#define PPC4xx_PCIL0_PMM1MA		0x014
+#define PPC4xx_PCIL0_PMM1PCILA		0x018
+#define PPC4xx_PCIL0_PMM1PCIHA		0x01C
+#define PPC4xx_PCIL0_PMM2LA		0x020
+#define PPC4xx_PCIL0_PMM2MA		0x024
+#define PPC4xx_PCIL0_PMM2PCILA		0x028
+#define PPC4xx_PCIL0_PMM2PCIHA		0x02C
+#define PPC4xx_PCIL0_PTM1MS		0x030
+#define PPC4xx_PCIL0_PTM1LA		0x034
+#define PPC4xx_PCIL0_PTM2MS		0x038
+#define PPC4xx_PCIL0_PTM2LA		0x03C
 
 extern u8 as1_readb(volatile u8 __iomem  *addr);
 extern void as1_writeb(u8 data, volatile u8 __iomem *addr);
 extern void ppc44x_reset_system(char *cmd);
 
+#ifdef CONFIG_PCI
+int ppc440epx_exclude_device(struct pci_controller *hose,
+		u_char bus, u_char devfn);
+int ppc440epx_add_bridge(struct device_node *dev);
+#endif
+
 #endif /* __POWERPC_PLATFORMS_44X_44X_H */

@@ -2,3 +2,7 @@ obj-$(CONFIG_44x)	:= misc_44x.o
 obj-$(CONFIG_EBONY)	+= ebony.o
 obj-$(CONFIG_BAMBOO) += bamboo.o
 obj-$(CONFIG_SEQUOIA)	+= sequoia.o
+
+ifeq ($(CONFIG_PCI),y)
+obj-$(CONFIG_440EPX)   += ppc440epx-pci.o
+endif

@@ -0,0 +1,192 @@
+/*
+ * PPC44x PCI host support
+ *
+ * Vitaly Bordug <vitb@kernel.crashing.org>
+ * Stefan Roese <sr@denx.de>
+ *
+ * Based on arch/ppc sequoia pci bits, that are
+ * Copyright 2006-2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * Based on bamboo.c from Wade Farnsworth <wfarnsworth@mvista.com>
+ *      Copyright 2004 MontaVista Software Inc.
+ *      Copyright 2006 AMCC
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/io.h>
+
+#include <mm/mmu_decl.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/pci-bridge.h>
+#include <asm/prom.h>
+
+#include "44x.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#ifdef CONFIG_PCI
+
+int ppc440epx_exclude_device(struct pci_controller *hose, u_char bus,
+			   u_char devfn)
+{
+	if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	return PCIBIOS_SUCCESSFUL;
+}
+
+inline void pci_writel(void *pci_reg_base, u32 offset, unsigned int val)
+{
+	writel(val, pci_reg_base + offset);
+}
+
+inline void pci_cfg_out(void *cfg, u32 offset, unsigned int value)
+{
+	out_le32((void *)((u32) cfg + offset), value);
+}
+
+inline u32 pci_cfg_in(void *cfg, u32 offset)
+{
+	return in_le32((void *)((u32) cfg + offset));
+}
+
+static void __init ppc440epx_setup_pci(struct pci_controller *hose,
+				     void *pci_reg_base, void *pci_cfg_base)
+{
+	unsigned long memory_size, pci_size = 0;
+	phys_addr_t pci_phys_base = 0;
+	phys_addr_t pci_pci_base = 0;
+	int i;
+
+	memory_size = total_memory;
+
+	/*
+	 * 440EPx has single memory region, we'll use it to configure phb
+	 */
+	for (i = 0; i < 3; i++)
+		if (hose->mem_resources[i].start) {
+			pci_phys_base = hose->mem_resources[i].start;
+			pci_pci_base = pci_phys_base - hose->pci_mem_offset;
+			pci_size =
+			    hose->mem_resources[i].end -
+			    hose->mem_resources[i].start;
+		}
+
+	if (pci_phys_base == 0) {
+		printk(KERN_ERR "PHB bridge memory region is not defined!\n");
+		return;
+	}
+
+	pci_cfg_out(pci_cfg_base, PPC4xx_PCI_CFGA_OFFSET,
+		    (pci_pci_base & 0xFFFFFFFF) | (PCI_COMMAND & 0xfc));
+	pci_cfg_out(pci_cfg_base, PPC4xx_PCI_CFGD_OFFSET,
+		    (pci_cfg_in(pci_cfg_base, PPC4xx_PCI_CFGD_OFFSET) |
+		     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+	/* Disable region first */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM0MA, 0);
+
+	/* PLB starting addr: 0x0000000180000000
+	 * We need just lower word to get the things work
+	 */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM0LA,
+		   pci_phys_base & 0xFFFFFFFF);
+
+	/* PCI start addr, 0x80000000 (PCI Address) */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM0PCILA,
+		   pci_pci_base & 0xFFFFFFFF);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM0PCIHA, 0);
+
+	/* Enable no pre-fetch, enable region */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM0MA,
+		   ((0xffffffff - pci_size) | 0x01));
+
+	/* Disable region one */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1MA, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1LA, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1PCILA, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1PCIHA, 0);
+
+	/* Disable region two */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1MA, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1LA, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1PCILA, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PMM1PCIHA, 0);
+
+	/* Now configure the PCI->PLB windows, we only use PTM1
+	 *
+	 * For Inbound flow, set the window size to all available memory
+	 * This is required because if size is smaller,
+	 * then Eth/PCI DD would fail as PCI card not able to access
+	 * the memory allocated by DD.
+	 */
+
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PTM1MS, 0);
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PTM1LA, 0);
+
+	memory_size = 1 << fls(memory_size - 1);
+
+	/* Size low + Enabled */
+	pci_writel(pci_reg_base, PPC4xx_PCIL0_PTM1MS,
+		   (0xffffffff - (memory_size - 1)) | 0x1);
+	eieio();
+}
+
+int __init ppc440epx_add_bridge(struct device_node *dev)
+{
+	int len;
+	struct pci_controller *hose;
+	const int *bus_range;
+	int primary = 1;
+	void *reg, *cfg;
+
+	/* Fetch host bridge registers address */
+	reg = of_iomap(dev, 1);
+	cfg = of_iomap(dev, 0);
+
+	DBG("Adding PCI host bridge %s\n reg %p cfg %p\n", dev->full_name, reg,
+	    cfg);
+
+	/* Get bus range if any */
+	bus_range = of_get_property(dev, "bus-range", &len);
+	if (bus_range == NULL || len < 2 * sizeof(int))
+		printk(KERN_WARNING "Can't get bus-range for %s, assume"
+		       " bus 0\n", dev->full_name);
+
+	pci_assign_all_buses = 1;
+	hose = pcibios_alloc_controller(dev);
+	if (!hose)
+		return -ENOMEM;
+
+	hose->first_busno = bus_range ? bus_range[0] : 0;
+	hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+	setup_indirect_pci_noremap(hose, (u32) cfg,
+				   (u32) (cfg + PPC4xx_PCI_CFGD_OFFSET), 0);
+
+	/* Interpret the "ranges" property */
+	/* This also maps the I/O region and sets isa_io/mem_base */
+	pci_process_bridge_OF_ranges(hose, dev, primary);
+	ppc440epx_setup_pci(hose, reg, cfg);
+
+	return 0;
+}
+#endif

@@ -52,6 +52,20 @@ static int __init sequoia_probe(void)
 
 static void __init sequoia_setup_arch(void)
 {
+#ifdef CONFIG_PCI
+	struct device_node *np;
+#endif
+
+	if (ppc_md.progress)
+		ppc_md.progress("ppc44x_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+	for (np = NULL; (np = of_find_compatible_node(np,
+					"pci", "ibm, 440epx")) != NULL;)
+		ppc440epx_add_bridge(np);
+	ppc_md.pci_exclude_device = ppc440epx_exclude_device;
+#endif
+
 }
 
 define_machine(sequoia) {

@@ -162,3 +162,17 @@ setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32
 	hose->ops = &indirect_pci_ops;
 	hose->indirect_type = flags;
 }
+
+/*
+ * For some reason, ioremap does not handle 2-nd way mapping well,
+ * causing system check while trying to access config space later
+ */
+void __init
+setup_indirect_pci_noremap(struct pci_controller *hose, u32 cfg_addr,
+		u32 cfg_data, u32 flags)
+{
+	hose->cfg_addr = (void *)cfg_addr;
+	hose->cfg_data = (void *)cfg_data;
+	hose->ops = &indirect_pci_ops;
+	hose->indirect_type = flags;
+}

@@ -99,6 +99,8 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
 
 extern void setup_indirect_pci(struct pci_controller* hose,
 			       u32 cfg_addr, u32 cfg_data, u32 flags);
+extern void setup_indirect_pci_noremap(struct pci_controller *hose,
+			       u32 cfg_addr, u32 cfg_data, u32 flags);
 extern void setup_grackle(struct pci_controller *hose);
 extern void __init update_bridge_resource(struct pci_dev *dev,
 					  struct resource *res);