Hi Ingo,
Please apply.
This series of patches fixes a build breakage and some minor issues
including oonverting spinlocks to raw ones, adding a need_resched_delayed
check, etc. for powerpc64.
This applies on top of linux-2.6.21 and patch-2.6.21-rt1.
Compile and boot tested for both PREEMPT_NONE and PREEMPT_RT on Celleb.
Compile tested for PREEMPT_DESKTOP.
Thanks in advance.
-- owa
TOSHIBA, Corprate Software Engineering Center.
Convert more spinlocks to raw ones for Celleb.
Signed-off-by: Tsutomu OWA <redacted>
-- owa
diff -rup linux-2.6.21-rt1/arch/powerpc/platforms/celleb/htab.c rt/arch/powerpc/platforms/celleb/htab.c
To reduce scheduling latecy by changing tlb flush size to 1.
Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s),
it takes a long time to flush tlbs and causes scheduing latency.
As I don't know how long it takes on other platforms, it would be better to
enclose it within #ifdef CONFIG_PPC_CELLEB.
Signed-off-by: Tsutomu OWA <redacted>
-- owa
diff -rup linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h rt/include/asm-powerpc/tlbflush.h
@@ -25,7 +25,11 @@ struct mm_struct;#include<linux/percpu.h>#include<asm/page.h>+#ifdef CONFIG_PREEMPT_RT+#define PPC64_TLB_BATCH_NR 1 /* Since tlb flush takes long time, reduce it to 1 when RT */+#else#define PPC64_TLB_BATCH_NR 192+#endif /* CONFIG_PREEMPT_RT */structppc64_tlb_batch{unsignedlongindex;
Oopps, Subject was wrong.... resending it. Sorry.
To reduce scheduling latecy by changing tlb flush size to 1.
Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s),
it takes a long time to flush tlbs and causes scheduing latency.
As I don't know how long it takes on other platforms, it would be better to
enclose it within #ifdef CONFIG_PPC_CELLEB.
Signed-off-by: Tsutomu OWA <redacted>
-- owa
diff -rup linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h rt/include/asm-powerpc/tlbflush.h
@@ -25,7 +25,11 @@ struct mm_struct;#include<linux/percpu.h>#include<asm/page.h>+#ifdef CONFIG_PREEMPT_RT+#define PPC64_TLB_BATCH_NR 1 /* Since tlb flush takes long time, reduce it to 1 when RT */+#else#define PPC64_TLB_BATCH_NR 192+#endif /* CONFIG_PREEMPT_RT */structppc64_tlb_batch{unsignedlongindex;
Add a need_resched_delayed() check.
This was pointed by Sergei Shtylyov;
http://ozlabs.org/pipermail/linuxppc-dev/2007-March/033148.html
Signed-off-by: Tsutomu Owa <redacted>
-- owa
diff -rup linux-2.6.21-rt1/arch/powerpc/kernel/idle.c rt/arch/powerpc/kernel/idle.c
From: Thomas Gleixner <hidden> Date: 2007-05-14 06:48:39
Tsutomu-san,
On Mon, 2007-05-14 at 15:38 +0900, Tsutomu OWA wrote:
Oopps, Subject was wrong.... resending it. Sorry.
To reduce scheduling latecy by changing tlb flush size to 1.
Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s),
it takes a long time to flush tlbs and causes scheduing latency.
As I don't know how long it takes on other platforms, it would be better to
enclose it within #ifdef CONFIG_PPC_CELLEB.
Yes, that might be appropriate. Can you add this and resend please ?
tglx
At Mon, 14 May 2007 08:51:46 +0200, Thomas Gleixner wrote:
On Mon, 2007-05-14 at 15:38 +0900, Tsutomu OWA wrote:
quoted
As I don't know how long it takes on other platforms, it would be better to
enclose it within #ifdef CONFIG_PPC_CELLEB.
Yes, that might be appropriate. Can you add this and resend please ?
Certainly, and thanks for your comment.
To reduce scheduling latecy by changing tlb flush size to 1.
Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s),
it takes a long time to flush tlbs and causes scheduing latency.
Signed-off-by: Tsutomu OWA <redacted>
-- owa
@@ -25,7 +25,12 @@ struct mm_struct;#include<linux/percpu.h>#include<asm/page.h>+#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)+/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */+#define PPC64_TLB_BATCH_NR 1+#else#define PPC64_TLB_BATCH_NR 192+#endif /* defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) */structppc64_tlb_batch{unsignedlongindex;
=A0#include <linux/percpu.h>
=A0#include <asm/page.h>
=A0
+#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)
+/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb=
With this code, you get silent side-effects of enabling PPC_CELLEB
along with another platform.
Maybe instead you should change the hpte_need_flush() to always flush
when running on the celleb platform and PREEMPT_RT is enabled.
Arnd <><
=A0#include <linux/percpu.h>
=A0#include <asm/page.h>
=A0
+#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)
+/* Since tlb flush takes long time on Celleb, reduce it to 1 when Cell=
eb && RT */
quoted
+#define PPC64_TLB_BATCH_NR 1
With this code, you get silent side-effects of enabling PPC_CELLEB
along with another platform.
Yeah, thank you for pointing it out.
I'll send revised patch later.
Maybe instead you should change the hpte_need_flush() to always flush
when running on the celleb platform and PREEMPT_RT is enabled.
At Mon, 14 May 2007 16:40:02 +0200, Arnd Bergmann wrote:
quoted
+#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)
+/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */
+#define PPC64_TLB_BATCH_NR 1
With this code, you get silent side-effects of enabling PPC_CELLEB
along with another platform.
Maybe instead you should change the hpte_need_flush() to always flush
when running on the celleb platform and PREEMPT_RT is enabled.
OK, how about this one?
thanks a lot!
Since flushing tlb needs expensive hypervisor call(s) on celleb,
always flush it on RT to reduce scheduling latency.
Signed-off-by: Tsutomu OWA <redacted>
-- owa
@@ -25,7 +25,12 @@ struct mm_struct;#include<linux/percpu.h>#include<asm/page.h>+#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)+/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */+#define PPC64_TLB_BATCH_NR 1+#else#define PPC64_TLB_BATCH_NR 192+#endif /* defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) */
With this code, you get silent side-effects of enabling PPC_CELLEB
along with another platform.
Maybe instead you should change the hpte_need_flush() to always flush
when running on the celleb platform and PREEMPT_RT is enabled.
I think it's wrong either way.... Maybe we can make it a variable and
measure how much we can reasonably do in a given time frame at
boot ? :-) Since it depends wether there's an hypervisor etc...
Ben.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2007-05-15 07:38:59
+
+#ifdef CONFIG_PREEMPT_RT
+ /*
+ * Since flushing tlb needs expensive hypervisor call(s) on celleb,
+ * always flush it on RT to reduce scheduling latency.
+ */
+ if (machine_is(celleb)) {
+ flush_tlb_pending();
+ return;
+ }
+#endif /* CONFIG_PREEMPT_RT */
+
if (i >= PPC64_TLB_BATCH_NR)
flush_tlb_pending();
}
Any reason to do that only on celleb ? :-)
Also, we might want to still batch, though in smaller amount. Have you measured
the time it takes ? We might want to modulate the amount based on wether we
are using native hash tables or an hypervisor.
Ben.
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: 2007-05-15 08:41:25
quoted
Have you measured
the time it takes ? We might want to modulate the amount based on wether we
are using native hash tables or an hypervisor.
Yes, here is the trace log. Accordint it, flushing 9 entries takes about 50us.
It means that flushing 192 (PPC64_TLB_BATCH_NR) entries takes 1ms.
Please note that tracing causes *roughly* 20-30% overhead, though.
I'm afraid I don't have numbers w/ native version, but I suppose you have :)
Actually I don't off hand but I'll try to get some.