[PATCH] ppc: Fix PCIX configuration of Ocotea & Taishan for > 512MB DDR
From: Stefan Roese <sr@denx.de>
Date: 2007-03-16 20:03:45
Subsystem:
the rest · Maintainer:
Linus Torvalds
[PATCH] ppc: Fix PCIX configuration of Ocotea & Taishan for > 512MB DDR Change the configuration of the PCIX PCI->PLB inbound memory window to be 2GB instead of 512kB. The comment already mentioned 2GB, but the code unfortunately didn't reflect this. Signed-off-by: Stefan Roese <sr@denx.de> --- commit 7eb6a3d9d0d0dadd5634d6c7c3fd262652076355 tree 620c232e5cf39d5cf905ec503f4fc86456cef104 parent 2553194704512d8a00d6e50b9e780ecc87d1ca2a author Stefan Roese [off-list ref] Fri, 16 Mar 2007 20:57:00 +0100 committer Stefan Roese [off-list ref] Fri, 16 Mar 2007 20:57:00 +0100 arch/ppc/platforms/4xx/ocotea.c | 2 +- arch/ppc/platforms/4xx/taishan.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 14780eb..626264a 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c@@ -178,7 +178,7 @@ ocotea_setup_pcix(void) /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); - PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); + PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); eieio(); }
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
index bb0253e..5d9af8d 100644
--- a/arch/ppc/platforms/4xx/taishan.c
+++ b/arch/ppc/platforms/4xx/taishan.c@@ -235,7 +235,7 @@ taishan_setup_pcix(void) /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); - PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); + PCIX_WRITEL(0x80000007, PCIX0_PIM0SA); PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); iounmap(pcix_reg_base);