I'm trying to write an EDAC driver for the mpc8560 board. I will need
to access the DDR error management registers, the L2 error management
registers, the PCI management registers, and also the related IRQs
(internal 0, 2, and 8). So I would like to insert some entries into
the 8560 fdt in order to parse them and map the hw irq to virq in
order to setup the platform device resources.
Below is what I was thinking the fdt should look like. Is that reasonable?
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
dram_control@2000 {
device_type = "edac";
compatible = "85xx";
reg = <2000 e5c>;
linux,phandle = <2000>;
interrupt-parent = <40000>;
interrupts = <2 1>;
};
l2_error@20e00 {
device_type = "edac";
compatible = "85xx";
reg = <20e00 5c>;
linux,phandle = <20e00>;
interrupt-parent = <40000>;
interrupts = <0 1>;
};
pci_error@8e00 {
device_type = "edac";
compatible = "85xx";
reg = <8e00 20>;
linux,phandle = <8e00>;
interrupt-parent = <40000>;
interrupts = <8 0>;
};
.....
--
-= Dave =-
On Jan 16, 2007, at 2:46 PM, Dave wrote:
I'm trying to write an EDAC driver for the mpc8560 board. I will need
to access the DDR error management registers, the L2 error management
registers, the PCI management registers, and also the related IRQs
(internal 0, 2, and 8). So I would like to insert some entries into
the 8560 fdt in order to parse them and map the hw irq to virq in
order to setup the platform device resources.
Below is what I was thinking the fdt should look like. Is that
reasonable?
I dont see the reason to introduce nodes that are specific to EDAC.
You should add nodes for the full device (which includes the error
mgmt). In the case of PCI the node should be there and fixing the
dts to report the proper irq is all that is needed.
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
dram_control@2000 {
device_type = "edac";
compatible = "85xx";
reg = <2000 e5c>;
expand to cover the full 4k allocated to ddr controller
linux,phandle = <2000>;
interrupt-parent = <40000>;
interrupts = <2 1>;
should be <2 2>
};
maybe something more generic like
memory-controller@2000 {
...
}
l2_error@20e00 {
device_type = "edac";
compatible = "85xx";
reg = <20e00 5c>;
linux,phandle = <20e00>;
interrupt-parent = <40000>;
interrupts = <0 1>;
should be <0 2>
};
Let's mimic the CPU cache node for this:
l2-cache@20000 {
device_type = "cache";
... (various cache properties, size, line size, etc.)
compatible = "85xx";
(Not sure if 85xx is the best for compatible)
reg = <20000 100>;
interrupt-parent = <40000>;
interrupts = <0 1>;
};
pci_error@8e00 {
device_type = "edac";
compatible = "85xx";
reg = <8e00 20>;
linux,phandle = <8e00>;
interrupt-parent = <40000>;
interrupts = <8 0>;
};
Use the existing pci node as I mentioned above.
- k
.....
--
-= Dave =-
On Tue, Jan 16, 2007 at 03:17:20PM -0600, Kumar Gala wrote:
On Jan 16, 2007, at 2:46 PM, Dave wrote:
quoted
I'm trying to write an EDAC driver for the mpc8560 board. I will need
to access the DDR error management registers, the L2 error management
registers, the PCI management registers, and also the related IRQs
(internal 0, 2, and 8). So I would like to insert some entries into
the 8560 fdt in order to parse them and map the hw irq to virq in
order to setup the platform device resources.
Below is what I was thinking the fdt should look like. Is that
reasonable?
I dont see the reason to introduce nodes that are specific to EDAC.
You should add nodes for the full device (which includes the error
mgmt). In the case of PCI the node should be there and fixing the
dts to report the proper irq is all that is needed.
quoted
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
dram_control@2000 {
device_type = "edac";
compatible = "85xx";
reg = <2000 e5c>;
expand to cover the full 4k allocated to ddr controller
quoted
linux,phandle = <2000>;
interrupt-parent = <40000>;
Probably best to have dtc assign the phandles, rather than doing them
explicitly, too. Less fragile if things move about.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson