I'm using an MVME6100 with Linux 2.6.14 and experiencing what I think is
a cache coherency problem. An external PCIX master performs a DMA
transfer of a well known data pattern into SDRAM, but when the device
driver goes to look at the data it is mostly okay, but occasionally has
garbage.
I'm allocating the memory using alloc_skb, then giving a PCI translated
pointer to the PCIX master. Since I think it is a cache coherency
problem, I tried to use the dma_cache_inv macro to invalidate the cache
before looking at the data, but realized that for this board, that
function does nothing since CONFIG_NOT_COHERENT_CACHE is undefined. So
questions:
1) Should the processor bus cache snooping actually work on an MVME6100?
E.g. is it correct that CONFIG_NOT_COHERENT_CACHE is undefined?
1a) Does this type of bus snooping work when a bus master physically
external to the PowerPC chip is doing the transfer?
2) If this really is a cache coherency problem, are there other cache
management functions available in ppc linux besides the dma_cache_inv,
dma_cache_wback, dma_cache_wback_inv macros I should be looking at?
Tim
Tim> I'm using an MVME6100 with Linux 2.6.14 and experiencing what=20
Tim> I think is a cache coherency problem. An external PCIX=20
Tim> master performs a DMA transfer of a well known data pattern=20
Tim> into SDRAM, but when the device driver goes to look at the=20
Tim> data it is mostly okay, but occasionally has garbage.
If the hardware is reliable, I think you are right. The cache coherency
problem.
Tim> I'm allocating the memory using alloc_skb, then giving a PCI=20
Tim> translated pointer to the PCIX master. Since I think it is a=20
Tim> cache coherency problem, I tried to use the dma_cache_inv=20
Tim> macro to invalidate the cache before looking at the data, but=20
Tim> realized that for this board, that function does nothing=20
Tim> since CONFIG_NOT_COHERENT_CACHE is undefined. So
Tim> questions:
If the CONFIG_NOT_COHERENT_CACHE is not set.
You are assuming and using the hardware cache coherency mechanism.
Tim> 1) Should the processor bus cache snooping actually work on=20
Tim> an MVME6100?
Tim> E.g. is it correct that CONFIG_NOT_COHERENT_CACHE is undefined?
Yes, you can undefine the CONFIG_NOT_COHERENT_CACHE, but you must
make sure the host bridge did the snooping setup for PCI inbound
transaction.
If you setup the snooping window, I think the host bridge will assert
/GLB signal
to processor. The processor will snoop the 60x/MPX bus to keep cache
coherence.
Also, you can define the CONFIG_NOT_COHERENT_CACHE, then you are
assuming
The system has not hardware coherency. You need use the software to keep
the cache
coherency.
Tim> 1a) Does this type of bus snooping work when a bus master=20
Tim> physically external to the PowerPC chip is doing the transfer?
As above, you must tell the bridge what address need snoop. If you did,
The proceesor will do snooping.
Tim> 2) If this really is a cache coherency problem, are there=20
Tim> other cache management functions available in ppc linux=20
Tim> besides the dma_cache_inv, dma_cache_wback,=20
Tim> dma_cache_wback_inv macros I should be looking at?
I think it is a cache coherency problem,
if you define the CONFIG_NOT_COHERENT_CACHE
You can get these functions, dma_map_single
-Dave