RE: MPC85xx PCI transfer disconnect

After scaning more logic analyzer captures, I noticed that 
occasionally the MPC85xx inserts additional wait states (by 
deasserting TRDY#) after only 32 bytes have been transferred. 
 So it definitely appears that (the way I have things 
configured now) there's a 20-80ns delay after 1 cache line is 
read, and the MPC85xx disconnects transfers that are larger 
than 2 cache lines.

There is one description about MRM cmd in the MPC85xx user manual.
[Memory read multiple] 
Similar to the memory-read command, but also causes a
prefetch of the next cache line (32 bytes).

How many masters in your PCI system? 
Maybe, you can tune the master latency timer of Tsi148 to get more bandwidth.
The latecy timer is locate at configuration space of your master.

Dave