L3 cache on Apple dual processor (7450 r 2.1) question

3 messages, 2 authors, 2006-06-20 · open the first message on its own page

L3 cache on Apple dual processor (7450 r 2.1) question

From: Till Wimmer <hidden>
Date: 2006-06-19 14:33:16

Hello,

i tried to enable the L3 cache on my dual 800MHz processor board (taken
from Quicksilver). I'm running the 2.6.8-3-powerpc-smp kernel from
Debian.

I changed the code for in core99_init_caches() in
arch/ppc/platforms/pmac_smp.c because the cache wasn't enabled by
default:

        if (cpu == 0){
                _set_L3CR(0);
                _set_L3CR(0x9F424340);
                core99_l3_cache = _get_L3CR();
                printk("CPU0: L3CR is %lx\n", core99_l3_cache);
        } else {
                printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
                _set_L3CR(0);
                _set_L3CR(core99_l3_cache);
		printk("CPU%d: L3CR is %lx\n", cpu, _get_L3CR());
        }
Now my questions are:
Is there anything else to do for getting the L3 cache working?
How can i check if the L3 is enabled? E.g. is there a benchmark program
which accounts for cache settings?

Thanx
Till

Re: L3 cache on Apple dual processor (7450 r 2.1) question

From: Olof Johansson <hidden>
Date: 2006-06-19 14:37:14

On Mon, Jun 19, 2006 at 04:17:04PM +0200, Till Wimmer wrote:
Now my questions are:
Is there anything else to do for getting the L3 cache working?
How can i check if the L3 is enabled? E.g. is there a benchmark program
which accounts for cache settings?
lmbench has testcases for memory latency testing.

http://www.bitmover.com/lmbench/


-Olof

Re: L3 cache on Apple dual processor (7450 r 2.1) question

From: Till Wimmer <hidden>
Date: 2006-06-20 13:27:55

Olof Johansson wrote:
On Mon, Jun 19, 2006 at 04:17:04PM +0200, Till Wimmer wrote:

 
quoted
Now my questions are:
Is there anything else to do for getting the L3 cache working?
How can i check if the L3 is enabled? E.g. is there a benchmark program
which accounts for cache settings?
   
lmbench has testcases for memory latency testing.
 
Thank you for the hint, i tested it and the results are deflating:
Most values are the same, but the communication bandwidths are worse 
with the L3 cache enabled? Therefore i think that my L3CR settings are 
wrong.

bg
Till


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