7 messages, 1 author, 2006-03-01 · open the first message on its own page
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:57:44
Greetings, The following patches are enhancements and/or fixes for the AMCC 440SP SoC and the Luan board. Most notably there is support for UART2 and the L2 Cache, as well as increased flexibility for the PCIX bridges. --Wade Farnsworth
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:45:53
This fixes the IRQ number for UART 2 on the 440SP and adds support to ibm440gx_get_clocks() for it. It also enables the UART on the Luan. --Wade Signed off by: Wade Farnsworth [off-list ref]
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:47:40
This adds the necessary structures for the UIC polarity and triggering on the 440SP & Luan. -Wade Signed off by: Wade Farnsworth [off-list ref]
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:50:23
This patch allows each bridge on the 440SP to be configured for both host and adapter mode. Previously, PCIX0 was configured for adapter mode only. Also fixes PCIXn_IO_BASE for PCIX1 and 2. Signed off by: Wade Farnsworth [off-list ref]
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:51:25
This adds L2 Cache support for the 440SP. --Wade Signed off by: Wade Farnsworth [off-list ref]
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:53:00
This fixes the clock and power management defines on the 440SP. --Wade Signed off by: Wade Farnsworth [off-list ref]
From: Wade Farnsworth <hidden>
Date: 2006-03-01 23:54:18
This fixes the defines for MTD support in the Luan platform file. --Wade Signed off by: Wade Farnsworth [off-list ref]