MPC5200 Rev. B

Has anyone experienced any issues with the Rev. B silicon for the MPC5200.  We
are seeing Linux hanging and are suspecting the SDRAM errata for Rev. B.  If we
disable the cache this seems to improve but will still crash over time in heavy
loads.  We have not seen any of these type issues with the original rev.

Matt

mgberry@ellipticity.com wrote:

Has anyone experienced any issues with the Rev. B silicon for the 
MPC5200.  We are seeing Linux hanging and are suspecting the SDRAM 
errata for Rev. B.  If we disable the cache this seems to improve 
but will still crash over time in heavy loads.  We have not seen any 
of these type issues with the original rev.

Are you sure you have revision B of the MPC5200?  Freescale has 
announced a "B" version, but I don't believe that any of them have 
hit the public yet.  There may be some engineering grade samples out 
there. (Let me know if you really do have "B" parts.  Freescale has 
been telling me "real soon now" since last year)

More likely you're seeing the "B" in the part number, as in 
MPC5200CBV400.  The chip revision is the "mask set" on the next line 
of printing.  The latest public version I know of is L25R.

The L25R version has a major bug that you basically can't use two CS 
pins for SDRAM, and the DDR implimentation is borderline at best.

Exactly what problems are seeing?  What hardware platform do you run 
on?  We're using an MPC5200 with SDR-SDRAM running at 132MHz (two 16 
bit SDRAM devices), and haven't seen any issues.

I don't know what bootloader you're using, but I believe uboot has 
basic memory testing built in.  This would allow you to isolate 
memory issues from software issues.

Eric

------------------------------------
Eric Johnson, Electrical Engineer
Advanced Communication Design
   7901 12th Avenue South
   Bloomington, MN 55425
Ph: 952-854-4000  Fax: 952-854-5774

Eric N. Johnson (ACD) wrote:

mgberry@ellipticity.com wrote:

quoted

Has anyone experienced any issues with the Rev. B silicon for the 
MPC5200.  We are seeing Linux hanging and are suspecting the SDRAM 
errata for Rev. B.  If we disable the cache this seems to improve but 
will still crash over time in heavy loads.  We have not seen any of 
these type issues with the original rev.

Are you sure you have revision B of the MPC5200?  Freescale has 
announced a "B" version, but I don't believe that any of them have hit 
the public yet.  There may be some engineering grade samples out 
there. (Let me know if you really do have "B" parts.  Freescale has 
been telling me "real soon now" since last year)

I can confirm that there are engineering samples of at least the first 
mask set of the Rev. B part floating around.  A friend sent me one:

 PPC5200CVR400 mask set M08A. 

Our local rep has hemming and hawing, too, which is getting very 
frustrating, knowing that other developers have had silicon in there 
hands for some time, and that several of the errata on the L25R mask set 
(PCI DMA arbitration, among them) have been causing us some serious 
headaches.

We have had very limited success with the Rev B engineering part, 
populated on a custom board.  Basically locking up at boot time when the 
DDR is enabled.  We're trying to isolate the problem to a hardware 
(board/part damaged) or software (are there changes to the memory 
controller configuration required for the Rev. B?). 

We do know that there are still errata on the first mask rev and that a 
second mask rev is in process.

Anyone else have anything to report?

-Nick