preliminary 750GX PLL control patch

2 messages, 2 authors, 2005-07-30 · open the first message on its own page

preliminary 750GX PLL control patch

From: Kevin Diggs <hidden>
Date: 2005-07-26 17:32:46

Hi,

         I've attached a patch that adds preliminary access to the HID1 
register in the 750GX (aka the PLL config register). The patch is 
against 2.4.30. It has been lightly tested on a PowerMac 8600 with a 
PowerLogix PowerForce 750GX cpu card.

         Depending on the values for the pllx_cfg field, this should 
work on the 750FX as well ... except for the stuff in idle_6xx.S. Since 
there are plenty of people on this list way more smarterer than me I was 
hoping someone could answer a question about the powersave modes that 
some of the PowerPC processors have:

         Since, as I understand it, the clock is shut off to much of the 
chip when a powersave mode is engaged does it really buy you that much 
to switch to a lower clock speed? Wouldn't you be better off shutting 
off the unused PLL?

         Also, please note that I am not very experienced creating 
patches so please use a backup of your source tree.

                                         kevin

Re: preliminary 750GX PLL control patch

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2005-07-30 16:21:27

On Tue, 2005-07-26 at 10:28 -0700, Kevin Diggs wrote:
Hi,

         I've attached a patch that adds preliminary access to the HID1 
register in the 750GX (aka the PLL config register). The patch is 
against 2.4.30. It has been lightly tested on a PowerMac 8600 with a 
PowerLogix PowerForce 750GX cpu card.

         Depending on the values for the pllx_cfg field, this should 
work on the 750FX as well ... except for the stuff in idle_6xx.S. Since 
there are plenty of people on this list way more smarterer than me I was 
hoping someone could answer a question about the powersave modes that 
some of the PowerPC processors have:

         Since, as I understand it, the clock is shut off to much of the 
chip when a powersave mode is engaged does it really buy you that much 
to switch to a lower clock speed? Wouldn't you be better off shutting 
off the unused PLL?

         Also, please note that I am not very experienced creating 
patches so please use a backup of your source tree.
Well... I replicated what darwin does here. I don't remember completely
but it's possible that there is some kind of CPU errata related to nap
and clock speed... or maybe it still makes a difference :)

You want to wakeup fast from nap too, so switching off/on the unused PLL
might not be that a good idea. But heh, you are welcome to try &
measure.

Ben.
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