On Thu, Mar 10, 2005 at 08:03:56AM -0800, Eugene Surovegin wrote:
On Thu, Mar 10, 2005 at 11:06:53AM +0100, Gerhard Jaeger wrote:
quoted
the patch has been posted in October last year (wow, thought it was in
december or so):
http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
I think it needs some cleanup to apply correctly, but the issue is still
the same - the RGMII bridge needs to be setup again after the EMAC has
been reset. This problem occurs, when the speed is != 100Mbs, then
the clocking for the phy is not correct.
I have attached an updated patch, which first checks the PHY speed, then
according to that speed the RGMII and ZMII will be setup...
[snip]
OK, from quick look it seems that this is infamous problem with PHYs
which don't generate Rx clock if there is no link.
Ok, good, I was just looking an wondering if it was the same issue.
Current driver works sometimes probably just by luck.
Gerhard, there is an experimental NAPI driver for 4xx at
http://kernel.ebshome.net (for current 2.4 & 2.6 BK trees). I recently
added full 440GX support. We (Matt and I) are thinking about
scraping the current driver and using my new version sometimes in the
future. It'd be great if you could find some time and try this new
driver on your board. Enable "PHY Rx clock workaround" in driver
config.
In the meantime, I'll see how this work-around works on some platforms
I have here.
Gerhard: what's the list of 4xx systems (and phys) you have tested
this against? I assume this patch is used on all 4xx platforms you
support in your distro?
On Thursday 10 March 2005 17:12, Matt Porter wrote:
On Thu, Mar 10, 2005 at 08:03:56AM -0800, Eugene Surovegin wrote:
quoted
On Thu, Mar 10, 2005 at 11:06:53AM +0100, Gerhard Jaeger wrote:
quoted
the patch has been posted in October last year (wow, thought it was in
december or so):
http://ozlabs.org/pipermail/linuxppc-embedded/2004-October/015811.html
I think it needs some cleanup to apply correctly, but the issue is still
the same - the RGMII bridge needs to be setup again after the EMAC has
been reset. This problem occurs, when the speed is != 100Mbs, then
the clocking for the phy is not correct.
I have attached an updated patch, which first checks the PHY speed, then
according to that speed the RGMII and ZMII will be setup...
[snip]
OK, from quick look it seems that this is infamous problem with PHYs
which don't generate Rx clock if there is no link.
Ok, good, I was just looking an wondering if it was the same issue.
quoted
Current driver works sometimes probably just by luck.
Gerhard, there is an experimental NAPI driver for 4xx at
http://kernel.ebshome.net (for current 2.4 & 2.6 BK trees). I recently
added full 440GX support. We (Matt and I) are thinking about
scraping the current driver and using my new version sometimes in the
future. It'd be great if you could find some time and try this new
driver on your board. Enable "PHY Rx clock workaround" in driver
config.
In the meantime, I'll see how this work-around works on some platforms
I have here.
Gerhard: what's the list of 4xx systems (and phys) you have tested
this against? I assume this patch is used on all 4xx platforms you
support in your distro?
In the end this patch is used on our 2.4 kernel series (with backported
2.6 EMAC driver). Tested on Walnut, Ebony, Ocotoea and two custom 440gx
boards, one PHY there is the mentionend DP83865 phy and the other phy
is the AMD79C875 (same as on Ebony and Ocotea). I thought, that this
problem is somewhat phy independant and more or less related to the
way, the phy is connected - here via GMII!
Ciao,
Gerhard