[PATCH] ppc32: update cpu state save/restore
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2005-01-18 01:34:29
Hi ! This patch updates the ppc32 cpu state save/restore code to deal with the Motorola/Freescale MPC7447A, used, among others, on recent Apple laptops. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Index: linux-work/arch/ppc/kernel/cpu_setup_6xx.S ===================================================================
--- linux-work.orig/arch/ppc/kernel/cpu_setup_6xx.S 2004-11-22 11:49:17.000000000 +1100
+++ linux-work/arch/ppc/kernel/cpu_setup_6xx.S 2005-01-17 13:49:16.268678952 +1100@@ -292,13 +292,15 @@ cmplwi cr2,r3,0x800c /* 7410 */ cmplwi cr3,r3,0x8001 /* 7455 */ cmplwi cr4,r3,0x8002 /* 7457 */ - cmplwi cr5,r3,0x7000 /* 750FX */ + cmplwi cr5,r3,0x8003 /* 7447A */ + cmplwi cr6,r3,0x7000 /* 750FX */ /* cr1 is 7400 || 7410 */ cror 4*cr1+eq,4*cr1+eq,4*cr2+eq /* cr0 is 74xx */ cror 4*cr0+eq,4*cr0+eq,4*cr3+eq cror 4*cr0+eq,4*cr0+eq,4*cr4+eq cror 4*cr0+eq,4*cr0+eq,4*cr1+eq + cror 4*cr0+eq,4*cr0+eq,4*cr5+eq bne 1f /* Backup 74xx specific regs */ mfspr r4,SPRN_MSSCR0
@@ -316,7 +318,7 @@ mfspr r4,SPRN_LDSTDB stw r4,CS_LDSTDB(r5) 1: - bne cr5,1f + bne cr6,1f /* Backup 750FX specific registers */ mfspr r4,SPRN_HID1 stw r4,CS_HID1(r5)
@@ -359,13 +361,15 @@ cmplwi cr2,r3,0x800c /* 7410 */ cmplwi cr3,r3,0x8001 /* 7455 */ cmplwi cr4,r3,0x8002 /* 7457 */ - cmplwi cr5,r3,0x7000 /* 750FX */ + cmplwi cr5,r3,0x8003 /* 7447A */ + cmplwi cr6,r3,0x7000 /* 750FX */ /* cr1 is 7400 || 7410 */ cror 4*cr1+eq,4*cr1+eq,4*cr2+eq /* cr0 is 74xx */ cror 4*cr0+eq,4*cr0+eq,4*cr3+eq cror 4*cr0+eq,4*cr0+eq,4*cr4+eq cror 4*cr0+eq,4*cr0+eq,4*cr1+eq + cror 4*cr0+eq,4*cr0+eq,4*cr5+eq bne 2f /* Restore 74xx specific regs */ lwz r4,CS_MSSCR0(r5)
@@ -404,7 +408,7 @@ mtspr SPRN_LDSTDB,r4 isync sync -2: bne cr5,1f +2: bne cr6,1f /* Restore 750FX specific registers * that is restore HID2 on rev 2.x and PLL config & switch * to PLL 0 on all