JTAG debug mechanism

5 messages, 4 authors, 2004-08-14 · open the first message on its own page

JTAG debug mechanism

From: Li Yang-r58472 <hidden>
Date: 2004-08-13 05:44:43

Hi,

I know this question is off topic, but I can't find a better place to ask.  I will be grateful if anyone can give me a hint or direct me to a reference.

As we know PowerPC use JTAG to debug CPU, which implements a Boundary-Scan mechanism.  It can manipulate any input/output signals of the CPU by a serial shift/scan process.  But my question is how it can read/write the core registers and system memory as implemented by most JTAG emulators.

Thanks,
Leo

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Re: JTAG debug mechanism

From: Dan Malek <hidden>
Date: 2004-08-13 06:26:42

On Aug 13, 2004, at 1:44 AM, Li Yang-r58472 wrote:
.... But my question is how it can read/write the core registers and
system memory as implemented by most JTAG emulators.
By using the Freescale COP implementation over the JTAG pins.
All debuggers do this.  Most of us don't care about such details,
we just buy the tools, plug them in and use them.


	-- Dan


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Re: JTAG debug mechanism

From: Song Sam <hidden>
Date: 2004-08-13 08:22:11

Li Yang-r58472 [off-list ref] wrote:
As we know PowerPC use JTAG to debug CPU, which
But 8xx use BDM to debug CPU.So I wonder in which
situation or chips should we use BDM and JATG and
WHY??? For a embedded developer,he could more concern
about this point than JATG implementation process,I
guess.:-)
implements a Boundary-Scan mechanism. It can manipulate any
input/output signals of the CPU by a serial shift/scan process. But my
question is how it can read/write the core registers and system memory
as implemented by most JTAG emulators.
Any input is warmly welcome!

Best regards,

Sam

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Re: JTAG debug mechanism

From: Mark Chambers <hidden>
Date: 2004-08-13 14:55:44

But 8xx use BDM to debug CPU.So I wonder in which
situation or chips should we use BDM and JATG and
WHY??? For a embedded developer,he could more concern
about this point than JATG implementation process,I
guess.:-)
As I think you know, JTAG and Boundary Scan are industry standards intended
primarily for
board manufacturing purposes.  Boundary Scan allows you access to the pins
on BGAs and other impossible-
to-reach pins on dense boards.  The Motorola CPUs simply borrow these same
pins for debug purposes, but
the internal debug logic is not directly related to JTAG.

Motorola does not release all the information about the debug interface on
all their processors.  However, the
BDM interface is well documented, and there is an open source project called
bdm4gdb.sourceforge.net, which
has the raw material for you to learn all you could want to know about bdm.

Good luck,
Mark Chambers


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Re: JTAG debug mechanism

From: Song Sam <hidden>
Date: 2004-08-14 07:53:27

Mark Chambers [off-list ref] wrote��
Motorola does not release all the information about the debug
interface on all their processors. However, the BDM interface
is well documented, and there is an open source project called
bdm4gdb.sourceforge.net, which has the raw material for you to learn
all you could want to know about bdm.
Thanks for giving this info.I enjoy it. :-)

Sam

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