Re: Large TLBs on 40x

On Tue, Aug 10, 2004 at 02:04:44AM -0400, Dan Malek wrote:

On Aug 9, 2004, at 10:21 PM, Josh Boyer wrote:

quoted

I have some boards I could test such a patch on.  Or is it a case of
"this isn't trivial to do"?

Ummmmm.....what are we talking about here?

Both MPC8xx, and IBM40x have configuration options for
pinning some (small) amount of kernel space.  You can choose
to enable this if you wish, I don't think it is normally enabled.
I've never found a benchmark that proved either was better,
but I left the code there for others to experiment with.

PPC40x no longer has this in 2.6. It has been deprecated by the dynamic
large tlb support. He's looking for an option (like nobats) to cause
kernel lowmem to not be mapped by large page entries.

So, to answer the original question, I would suggest a patch
that that uses a 'noltlb' cmdline option, then skips the PPC40x
large page mapping in 4xx_mmu.c based on that. See the code
that implements 'nobats' for an example.

-Matt

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On Aug 10, 2004, at 10:35 AM, Matt Porter wrote:

PPC40x no longer has this in 2.6.

Oh, I see now.

So, to answer the original question, I would suggest a patch
that that uses a 'noltlb' cmdline option,

Yes, that would work.

Thanks for the info.


	-- Dan


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On Tue, 2004-08-10 at 09:35, Matt Porter wrote:

On Tue, Aug 10, 2004 at 02:04:44AM -0400, Dan Malek wrote:

quoted

On Aug 9, 2004, at 10:21 PM, Josh Boyer wrote:

quoted

I have some boards I could test such a patch on.  Or is it a case of
"this isn't trivial to do"?

Ummmmm.....what are we talking about here?

Both MPC8xx, and IBM40x have configuration options for
pinning some (small) amount of kernel space.  You can choose
to enable this if you wish, I don't think it is normally enabled.
I've never found a benchmark that proved either was better,
but I left the code there for others to experiment with.

PPC40x no longer has this in 2.6. It has been deprecated by the dynamic
large tlb support. He's looking for an option (like nobats) to cause
kernel lowmem to not be mapped by large page entries.

So, to answer the original question, I would suggest a patch
that that uses a 'noltlb' cmdline option, then skips the PPC40x
large page mapping in 4xx_mmu.c based on that. See the code
that implements 'nobats' for an example.

Hm...  like this?  Against 2.6.8-rc4.

thx,
josh


diff -Naur -x '*.swp' linux-2.6.orig/arch/ppc/mm/4xx_mmu.c linux-2.6/arch/ppc/mm/4xx_mmu.c

--- linux-2.6.orig/arch/ppc/mm/4xx_mmu.c	2004-06-16 00:18:37.000000000 -0500
+++ linux-2.6/arch/ppc/mm/4xx_mmu.c	2004-08-11 08:25:11.000000000 -0500

@@ -52,6 +52,7 @@
 #include <asm/setup.h>
 #include "mmu_decl.h"

+extern int __map_without_ltlbs;
 /*
  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  */

@@ -102,6 +103,10 @@
 	p = PPC_MEMSTART;
 	s = 0;

+	if (__map_without_ltlbs) {
+		return s;
+	}
+
 	while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) {
 		pmd_t *pmdp;
 		unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;

diff -Naur -x '*.swp' linux-2.6.orig/arch/ppc/mm/init.c linux-2.6/arch/ppc/mm/init.c

--- linux-2.6.orig/arch/ppc/mm/init.c	2004-08-11 08:03:55.000000000 -0500
+++ linux-2.6/arch/ppc/mm/init.c	2004-08-11 08:11:24.000000000 -0500

@@ -104,6 +104,7 @@
  * -- Cort
  */
 int __map_without_bats;
+int __map_without_ltlbs;

 /* max amount of RAM to use */
 unsigned long __max_memory;

@@ -204,6 +205,10 @@
 		__map_without_bats = 1;
 	}

+	if (strstr(cmd_line, "noltlb")) {
+		__map_without_ltlbs = 1;
+	}
+
 	/* Look for mem= option on command line */
 	if (strstr(cmd_line, "mem=")) {
 		char *p, *q;

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On Aug 11, 2004, at 9:50 AM, Josh Boyer wrote:

Hm...  like this?  Against 2.6.8-rc4.

Does it work the way you want it now?

	-- Dan


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On Wed, 2004-08-11 at 10:30, Dan Malek wrote:

On Aug 11, 2004, at 9:50 AM, Josh Boyer wrote:

quoted

Hm...  like this?  Against 2.6.8-rc4.

Does it work the way you want it now?

Yep, tested it on my board.  It's not the end goal I am looking for, but
it's a good starting point.

Basically, what I would like to get eventually is large TLBs + protected
kernel text pages.  Like you and Matt pointed out, there are issues with
that.  If it can't be done, then at least I can use this patch to
protect the kernel text pages easily.  Sometimes protection is more
important than performance.  Especially when I am hacking on stuff ;).

Thanks for the help.

josh


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On Aug 11, 2004, at 1:58 PM, Josh Boyer wrote:

Yep, tested it on my board.  It's not the end goal I am looking for,
but
it's a good starting point.

Ummm...OK.

Basically, what I would like to get eventually is large TLBs +
protected
kernel text pages.  Like you and Matt pointed out, there are issues
with
that.  If it can't be done, .....

It can be done, just not easily.  Requires boundary/alignment of
text/data
and set up of the large TLBs.  Then, there is the issue with wanting the
same feature with loadable modules......

.......  Sometimes protection is more
important than performance.  Especially when I am hacking on stuff ;).

Well, you have the option now.  Have fun!


	-- Dan


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