Re: EDK6.1 vs. EDK3.2 clarification

Hi there,

Added configuration options to Linux config.in to control (actual names
are slightly different for internal naming convention):

	CACHE_MODE	-	Toggle these
	CACHE_REAL	-	Real mode cacheing enabled
	CACHE_KERNEL	-	Kernel pages cacheing enabled
	CACHE_USER	-	User pages cacheing enabled

The system now boots if I disable all cacheing and it seems to be ok.
However this only partially helps me and I still welcome input.

Anyone know of any particular reason why this Memec Insight board would
dislike cacheing being enabled especially with EDK6.1 hardware?

I would love to hand validate the cache contents and this kind of thing
but the Xilinx documentation is not good. The Xilinx XMD FAQ says that
icachestartadr is a command when in fact it is a parameter to ppcconnect
and then fails to provide an actual example of its use. *Sigh*.

Cheers,

Jon.


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Hi there,

I thought it prudent to update anyone who later reads this thread as to
the cause and outcome of this issue which was ongoing for a while.

It turns out that I had not correctly initialised the cache controller
in my firmware and today was able to prove that this had worked on the
old hardware generated with EDK3.2 however this was not the case with
EDK6.1 for whatever reason. It was not the Linux kernel at fault.

Perhaps I could moan about the various documentation and other issues
but it comes down to a bit of code which got changed at some point,
continued to work ok but later caused a hiccup with new hardware as the
data cache not being properly flushed on startup resulted in fun.

Bottom line is I now once more have a fully working Insight Memec V2P
port with EDK6.1 hardware and our custom modules are now in again.

I think someone else had similar symptoms...

Cheers,

Jon.

P.S. Thanks for reading.

P.P.S. I am going to FOSDEM in the morning if anyone cares.


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