Hi,
I'm programming an embedded device (with PPC405GP/EP) that has to access the
pci bus and there may be cases that there is no one listening there and a
timeout occurs which results in a machine check. Until now I used a eieio
operation with an exception handler after the actual io operation and this
seems to work. Current kernels contain a twi/isync/nop sequence. What are
the reasons for this sequence instead of an eieio? Is it only needed on
some processors? Is there a document that describes this special
sequence in more detail?
Thanks in advance,
Ronald
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Ronald Wahl writes:
I'm programming an embedded device (with PPC405GP/EP) that has to access the
pci bus and there may be cases that there is no one listening there and a
timeout occurs which results in a machine check. Until now I used a eieio
operation with an exception handler after the actual io operation and this
seems to work. Current kernels contain a twi/isync/nop sequence. What are
the reasons for this sequence instead of an eieio? Is it only needed on
some processors? Is there a document that describes this special
sequence in more detail?
The sequence was determined experimentally. The 601 was the worst in
terms of containing where the machine check would happen after a bad
access. The idea is that the twi is intended to create a dependency
on the value read, such that the processor doesn't know if the
instruction will generate an exception until the data comes back (in
fact the particular form of the twi instruction that I use won't ever
generate an exception, but fortunately the 601 isn't smart enough to
recognize that). The isync is then meant to stop the cpu until all
previous instructions have been executed to the point where the cpu
knows whether they will generate an exception or not. The nop is
there because the machine check can still occur on the instruction
after the isync on 601 (IIRC).
As I recall, the 604 was better but still needed more than just an
eieio or sync, and the G3 and G4 just needed an eieio or sync.
Paul.
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