On Thu, Sep 25, 2003 at 01:15:15PM -0500, Bret Indrelee wrote:
I've read through the old thread about short DMAs, but still there are
things that aren't clear to me.
What exactly is the issue?
The issue is confined to processors which do not support hardware
snooping of the external bus. In this case, management of the
caches is performed in software. Software cache management is
has a granularity of the processor's cache line size. When a
buffer is allocated using the allowed methods (as defined in
DMA-mapping.txt) to obtain memory for use in DMA, there is
no guarantee that the buffer is cacheline aligned. Imagine
one buffer allocated for internal driver management and another
buffer allocated for inbound DMA transactions from a bus
master. They can share the same cacheline. Inbound DMA
read transaction occurs, the usual streaming DMA API call is
made, and the platform-specific implementation invalidates the
entire cacheline. This could corrupt the contents of the
allocated management buffer that is being accessed by the CPU
only.
As I understand it, if there is a DMA to the same cache line as something
that the CPU is referencing, you've got a cache problem.
On a certain type of processors, yes.
Does it matter what type of transfer the PCI device is doing? If it
always does 32-bit burst memory write transfers instead of memory
write & invalidate does that make a difference?
Right now, I'm interested in the PPC and x86 compatible (Pentium,
Pentium 4, Geode) systems, trying to understand the differences and
requirements of each.
Which PPCs? Classic PPC != PPC8xx != PPC40x != Book E PPC. :)
PPC8xx and PPC4xx require software cache coherency. If you want
your products to work on PPC44x (I hope you do, they are targetted
at markets where qlogic storage controllers are used) ensuring that
your DMA buffers are cacheline aligned at the head/tail is
important.
-Matt
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On Thu, 25 Sep 2003, Matt Porter wrote:
On Thu, Sep 25, 2003 at 01:15:15PM -0500, Bret Indrelee wrote:
quoted
I've read through the old thread about short DMAs, but still there are
things that aren't clear to me.
What exactly is the issue?
The issue is confined to processors which do not support hardware
snooping of the external bus. In this case, management of the
caches is performed in software.
It is trying to figure out which systems have these sort of issues
that I'm currently puzzling through. Where the heck should I expect
to find this in the databooks for the various products?
[ snip ]
quoted
Right now, I'm interested in the PPC and x86 compatible (Pentium,
Pentium 4, Geode) systems, trying to understand the differences and
requirements of each.
Which PPCs? Classic PPC != PPC8xx != PPC40x != Book E PPC. :)
My immediate concern is 8245 and the Intel/Pentium style processors.
In the near term for PPC, the 8245 and maybe 405E.
PPC8xx and PPC4xx require software cache coherency. If you want
your products to work on PPC44x (I hope you do, they are targetted
at markets where qlogic storage controllers are used) ensuring that
your DMA buffers are cacheline aligned at the head/tail is
important.
It looked like on the PPC if I aligned for 32 byes (0x20), that should
handle it for now. This is for embedded, not the HBA controller, so I
shouldn't need to worry about CONFIG_PPC64BRIDGE.
On Pentium, I have to figure out if they do the snooping or not. I
suspect that they do, but finding cache coherency problems is bad
enough that I need a more definitive answer than that.
-Bret
--
Bret Indrelee QLogic Corporation
Bret.Indrelee@qlogic.com 6321 Bury Drive, St 13, Eden Prairie, MN 55346
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At 12:56 PM 9/25/2003, Matt Porter wrote:
When a buffer is allocated using the allowed methods (as defined in
DMA-mapping.txt) to obtain memory for use in DMA, there is
no guarantee that the buffer is cacheline aligned.
Hmm, I don't think this is true.
DMA-mapping.txt explicitly states that pci_alloc_consistent() returns
aligned memory buffer:
" ... The cpu return address and the DMA bus master address are both
guaranteed to be aligned to the smallest PAGE_SIZE order which
is greater than or equal to the requested size. This invariant
exists (for example) to guarantee that if you allocate a chunk
which is smaller than or equal to 64 kilobytes, the extent of the
buffer you receive will not cross a 64K boundary..."
I think it's safe to assume that PAGE_SIZE alignment also guarantees
cacheline alignment for all existing CPUs.
Eugene.
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On Thu, 25 Sep 2003, Eugene Surovegin wrote:
At 12:56 PM 9/25/2003, Matt Porter wrote:
quoted
When a buffer is allocated using the allowed methods (as defined in
DMA-mapping.txt) to obtain memory for use in DMA, there is
no guarantee that the buffer is cacheline aligned.
Hmm, I don't think this is true.
DMA-mapping.txt explicitly states that pci_alloc_consistent() returns
aligned memory buffer:
It has been cut from the conversation, but I'm using streaming DMA
mappings. Specifically, pci_map_single() and pci_unmap_single().
My reading of the 2.4 DMA-mapping.txt is that use of pci_alloc_consistent()
is specific to Consistent DMA mappings. Same for the pci_pool_ interface.
-Bret
--
Bret Indrelee QLogic Corporation
Bret.Indrelee@qlogic.com 6321 Bury Drive, St 13, Eden Prairie, MN 55346
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