Re: Unstable MPC8245 board

2 messages, 2 authors, 2003-02-26 · open the first message on its own page

Re: Unstable MPC8245 board

From: William A. Gatliff <hidden>
Date: 2003-02-26 01:34:37

Chris:

I'm not familiar with uMON, but I would guess it has some memory tests
in it.  Can you do burst reads/writes inside of uMON reliably?
Good question.  I have the source, I could add such a test.  (uMON has
a memory test, but it's a "walking ones and zeros" for verifying
hardware connectivity, not all that other stuff that's a problem with
SDRAMs).

What's a C construct that would virtually guarantee a burst read or
write?
Without knowing anything else, from what I see here, I'm guessing that
your problem is related to memory.  But testing outside of the kernel
will definitely help to rule that out.
Ok.  Thanks, that's a start...


b.g.
--
Bill Gatliff
http://billgatliff.com

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Re: Unstable MPC8245 board

From: Jan Damborsky <hidden>
Date: 2003-02-26 16:02:44

William A. Gatliff wrote:

 >What's a C construct that would virtually guarantee a burst read or
 >write?
 >
 >
I use MPC8xx and I had some problem with RWM bursting a two month ago.
PPC core uses bursting in several situations, not always.
For example, with I-cache and D-cache disabled, there are no bursts when
reading
instructiontions or reading or writting data from or to RWM, there are
only single beat
read or write cycles occuring on bus.
When enabled I-cache or D-cache in write-through mode, there are only
burst reads used,
no burst writes. In order to force PPC core to use burst-write cycles,
it is necessary to enable
D-cache working in copyback mode.
So when I want to test burst reads and burst writes:
[1] I enable D-cache in copyback mode (not so trivial as enable only
I-cache working)
[2] allocate a large array of longs (for example ten times more then
size of D-cache is)
[3] writting pseudo random data to this array.
[4] Verifying written data.
What happens:
When writting data, these are stored in D-cache until there is no free
place in D-cache.
Then when writting more data, older data from D-cache are stored in RWM
by means
of burst writes in order to make free place for newer data.
When verifiyng, data are read to cache from RWM by means of burst reads.
It is only a little example I used.
                                                                      HANYS


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