Re: 405GP external master

There's an app note at IBM about this:

http://www->

3.ibm.com/chips/techlib/techlib.nsf/techdocs/B60C93EB27F44B0F87256AAF005E788F/$file/405DMAPerformance02.pdf

--Chris

This appnote details the timing for DMA transfers, not
external masters.  I'm hoping that external masters
can result in better throughput than DMA.  With DMA,
you are limited to about 35 MB/sec max.  I need about
twice that bandwidth.

The user guide has timing diagrams for burst accesses
on the external bus.  If external masters and 405GP
can perform sustained, back-to-back burst transfers by
an external master, I should be able to hit my
targets.

Question is whether the 405GP can sustain continuous
burst transactions from an external master, or whether
there are other internal limitations which would
prevent me from hitting 70 MB/sec throughput from
SDRAM<->external master.

Thanks.


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