Re: very minor 405GP and 405GPr PCI difference

6 messages, 3 authors, 2002-10-09 · open the first message on its own page

Re: very minor 405GP and 405GPr PCI difference

From: Matt Porter <hidden>
Date: 2002-10-03 15:14:39

On Thu, Oct 03, 2002 at 11:10:44AM +1000, David Gibson wrote:
On Wed, Oct 02, 2002 at 10:03:12AM -0700, Matt Porter wrote:
quoted
That's exactly the problem.  If your world is filled with the
standard IBM reference platforms then a simple single host PCI
bridge in "CHRP-style" mapping probably seems reasonable.

In reality, it's necessary to design PCI host bridge library
code such that it can be called in a board-specific way to allow
for window mappings in "wacky" systems with 2 or more PCI connected
processors.  This is very common.
Ok, I can see why you'd want a different PCI mapping for that.

For boards like this, would it be sufficient for the generic code to
set up PMM0 and PTM1 with the standard mapping, then let the board
code use the remaining PMMs and PTMs for additional mappings?
In my book, that removes flexibility which is something I'm a
big believer in when it comes to embedded stuffs.  I'd prefer
to have something like:

	ibm_pci_init(<default_or_custom_map_flag>, <window_struct_ptr>)

If you want the default CHRP map you call like this:

	ibm_pci_init(IBM_PCI_DEFAULT_MAP, NULL);

If you want a custom map you fill out a window reg struct and do:

	ibm_pci_init(IBM_PCI_CUSTOM_MAP, &my_win_struct);

The implementation of the init function can be as simple as
just taking the values of the custom win struct and programming
verbatim into the PMMs and PTMs, or eventually one can get
fancy and provide a little more abstraction where one could
pass window start/end values and the code would do some range
checking a la pplus_common.c.

Since there's such an incredible amount of cleanup work to do
for 4xx, I think a bare bones back end implementation is more
than sufficient.  I should provide an example of this for
the 440gp/gx pcix logic, but having 440 stable seemed a bit
more important first. :)
quoted
This is where the current flow of having a common thread of excecution
falls apart (ppc4xx_setup).  40x really should be following the model
of the embedded 7xx/74xx system where each <board>.c would call to a
PCI library with some parameters to set up a desired set of window
mappings.  It's possible to have a default common case to set up
a CHRP-like mapping.
I agree absolutely.  The current flow of control of the board stuff is
a ghastly horrible mess.
Aha!  Good.
quoted
We've had some threads in the past about the limitations of using
this "common flow" design in 4xx.  I believe there was some agreement
that it is a limiting way to do things.  I do recall that Dan said
it was only this way because he copied the 826x flow and it probably
didn't make sense anymore for 4xx.  If there's no serious objections
I'm suggesting that this is where we go in the 2.5 4xx reorg.
Quite.  In fact I recall suggesting a re-org along these lines some
time ago, but then I got busy and didn't have time to actually send
patches.  I seem to recall there was some resistance to such a re-org
at the time.
Hrm, I will have to reread some of threads I saved.  I only recalled
some agreement from Dan that it probably didn't make sense any longer
and a tangential issue regarding the desire to build a single image
with multiple 4xx targets.  Something that I, incidentally, believe
is a waste of time since kernels can be built so quickly.

Regards,
--
Matt Porter
porter@cox.net
This is Linux Country. On a quiet night, you can hear Windows reboot.

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: very minor 405GP and 405GPr PCI difference

From: David Gibson <hidden>
Date: 2002-10-04 02:48:32

On Thu, Oct 03, 2002 at 08:14:39AM -0700, Matt Porter wrote:
On Thu, Oct 03, 2002 at 11:10:44AM +1000, David Gibson wrote:
quoted
On Wed, Oct 02, 2002 at 10:03:12AM -0700, Matt Porter wrote:
quoted
That's exactly the problem.  If your world is filled with the
standard IBM reference platforms then a simple single host PCI
bridge in "CHRP-style" mapping probably seems reasonable.

In reality, it's necessary to design PCI host bridge library
code such that it can be called in a board-specific way to allow
for window mappings in "wacky" systems with 2 or more PCI connected
processors.  This is very common.
Ok, I can see why you'd want a different PCI mapping for that.

For boards like this, would it be sufficient for the generic code to
set up PMM0 and PTM1 with the standard mapping, then let the board
code use the remaining PMMs and PTMs for additional mappings?
In my book, that removes flexibility which is something I'm a
big believer in when it comes to embedded stuffs.  I'd prefer
to have something like:
On the other hand, it adds simplicity, which I'm a big believer in
generally.  Nonetheless, point taken.
	ibm_pci_init(<default_or_custom_map_flag>, <window_struct_ptr>)

If you want the default CHRP map you call like this:

	ibm_pci_init(IBM_PCI_DEFAULT_MAP, NULL);

If you want a custom map you fill out a window reg struct and do:

	ibm_pci_init(IBM_PCI_CUSTOM_MAP, &my_win_struct);
This approach would fall out naturally if the basic init structure is
re-organised as we both think it should be (i.e. making the board
files have top-level control).  As an interim measure (to remove the
bug that is in many versions, and discourage its further propagation),
though, how about the patch below.

It is much like my previous patch, but allows the board to override
the setup if CONFIG_BOARD_PCI_MAPPING is defined.

diff -urN /home/dgibson/kernel/linuxppc-2.5/arch/ppc/kernel/4xx/ppc405_pci.c linux-bluefish/arch/ppc/kernel/4xx/ppc405_pci.c
--- /home/dgibson/kernel/linuxppc-2.5/arch/ppc/kernel/4xx/ppc405_pci.c	2002-10-04 10:36:17.000000000 +1000
+++ linux-bluefish/arch/ppc/kernel/4xx/ppc405_pci.c	2002-10-04 12:29:25.000000000 +1000
@@ -53,7 +53,6 @@
 #include <asm/ibm_ocp_pci.h>


-extern void bios_fixup(struct pci_controller *, struct pcil0_regs *);
 extern int ppc405_map_irq(struct pci_dev *dev, unsigned char idsel,
 			  unsigned char pin);
@@ -112,6 +111,114 @@
 	return (bus == 0 && devfn == 0);
 }

+static void __init
+configure_host_bridge(struct pci_controller *hose, struct pcil0_regs *pcip)
+{
+#ifdef CONFIG_BOARD_PCI_MAPPING
+	extern void bios_fixup(struct pci_controller *, struct pcil0_regs *);
+
+	/* The board wants to control the PCI configuration, let it
+	 * set up the bridge */
+
+	bios_fixup(hose, pcip);
+#elif CONFIG_BIOS_FIXUP
+	unsigned int bar_response, bar;
+
+	/* Otherwise, just set up the "standard" PCI mapping:
+	 *
+	 *  PLB addr             PCI memory addr
+	 *  ---------------------       ---------------------
+	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
+	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
+	 *
+	 *  PLB addr             PCI io addr
+	 *  ---------------------       ---------------------
+	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
+	 */
+
+#ifdef DEBUG
+	int i;
+
+	printk(KERN_DEBUG "ioremap PCLIO_BASE = 0x%p\n", pcip);
+	printk(KERN_DEBUG "PCI bridge regs before fixup \n");
+	for (i = 0; i <= 3; i++) {
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
+	}
+	printk(KERN_DEBUG " ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
+	printk(KERN_DEBUG " ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
+	printk(KERN_DEBUG " ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
+	printk(KERN_DEBUG " ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
+#endif
+
+	/* First set up the PLB->PCI window, we only use PMM0 */
+
+	/* Disable region first */
+	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
+	/* PLB starting addr, PCI: 0x80000000 */
+	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
+	/* PCI start addr, 0x80000000 */
+	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
+	/* 512MB range of PLB to PCI */
+	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
+	/* Enable no pre-fetch, enable region */
+	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
+						(PPC405_PCI_UPPER_MEM -
+						 PPC405_PCI_MEM_BASE)) | 0x01));
+
+	/* Disable region one */
+	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
+	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
+
+	/* Disable region two */
+	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
+	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
+
+	/* Now configure the PCI->PLB windows, we only use PTM1 */
+	out_le32((void *) &(pcip->ptm1ms), 0x00000000); /* first disable */
+	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* base address */
+	out_le32((void *) &(pcip->ptm1ms), 0x80000001); /* re-enable */
+	out_le32((void *) &(pcip->ptm2ms), 0x00000000); /* disable PTM2 */
+
+	/* Zero config bars */
+	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+		early_write_config_dword(hose, hose->first_busno,
+					 PCI_FUNC(hose->first_busno), bar,
+					 0x00000000);
+		early_read_config_dword(hose, hose->first_busno,
+					PCI_FUNC(hose->first_busno), bar,
+					&bar_response);
+		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
+		    hose->first_busno, PCI_SLOT(hose->first_busno),
+		    PCI_FUNC(hose->first_busno), bar, bar_response);
+	}
+	/* end work arround */
+
+#ifdef DEBUG
+	printk(KERN_DEBUG "PCI bridge regs after fixup \n");
+	for (i = 0; i <= 3; i++) {
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
+		printk(KERN_DEBUG " pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
+	}
+	printk(KERN_DEBUG " ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
+	printk(KERN_DEBUG " ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
+	printk(KERN_DEBUG " ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
+	printk(KERN_DEBUG " ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
+
+#endif /* DEBUG */
+#endif /* CONFIG_BIOS_FIXUP */
+}
+
 void
 ppc4xx_find_bridges(void)
 {
@@ -143,10 +250,8 @@

 	pcip = ioremap((unsigned long) ocp_get_paddr(OCP_FUNC_PCI, 0), PAGE_SIZE);
 	if (pcip != NULL) {
+		configure_host_bridge(hose_a, pcip);

-#if defined(CONFIG_BIOS_FIXUP)
-		bios_fixup(hose_a, pcip);
-#endif
 		new_pmm_min = 0xffffffff;
 		for (reg_index = 0; reg_index < 3; reg_index++) {
 			tmp_size = in_le32((void *) &(pcip->pmm[reg_index].ma));	// *_PMM0MA
diff -urN /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/ash.c linux-bluefish/arch/ppc/platforms/4xx/ash.c
--- /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/ash.c	2002-10-04 10:36:17.000000000 +1000
+++ linux-bluefish/arch/ppc/platforms/4xx/ash.c	2002-10-04 11:30:04.000000000 +1000
@@ -95,137 +95,6 @@
 }

 void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 2; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dpcila\t0x%x\n", i,
-		       in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dpciha\t0x%x\n", i,
-		       in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-
-#endif
-	if (ppc_md.progress)
-		ppc_md.progress("bios_fixup(): enter", 0x800);
-
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-
-	/* Enable PTM1 and PTM2, mapped to PLB address 0. */
-
-	out_le32((void *) &(pcip->ptm1la), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000001);
-	out_le32((void *) &(pcip->ptm2la), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000001);
-
-	/* Write zero to PTM1 BAR. */
-
-	early_write_config_dword(hose, hose->first_busno,
-				 PCI_FUNC(hose->first_busno),
-				 PCI_BASE_ADDRESS_1,
-				 0x00000000);
-
-	/* Disable PTM2 (unused) */
-
-	out_le32((void *) &(pcip->ptm2la), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* end work arround */
-	if (ppc_md.progress)
-		ppc_md.progress("bios_fixup(): done", 0x800);
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 2; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dla\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dpcila\t0x%x\n", i,
-		       in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dpciha\t0x%x\n", i,
-		       in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-
-
-#endif
-}
-
-void __init
 board_io_mapping(void)
 {
 	io_block_mapping(ASH_RTC_VADDR, ASH_RTC_PADDR, ASH_RTC_SIZE, _PAGE_IO);
diff -urN /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/ep405.c linux-bluefish/arch/ppc/platforms/4xx/ep405.c
--- /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/ep405.c	2002-10-04 10:36:17.000000000 +1000
+++ linux-bluefish/arch/ppc/platforms/4xx/ep405.c	2002-10-04 11:30:26.000000000 +1000
@@ -69,73 +69,6 @@
 }

 void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 */
-
-	/* Disable region zero first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Configure PTM (PCI->PLB) region 1 */
-	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
-	/* Disable PTM region 2 */
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end work arround */
-}
-
-void __init
 board_io_mapping(void)
 {
 	bd_t *bip = (bd_t *) __res;
diff -urN /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/rainier.c linux-bluefish/arch/ppc/platforms/4xx/rainier.c
--- /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/rainier.c	2002-09-19 16:08:06.000000000 +1000
+++ linux-bluefish/arch/ppc/platforms/4xx/rainier.c	2002-10-01 15:05:42.000000000 +1000
@@ -109,90 +109,6 @@
 }

 void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/*region one used bu rainier*/
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x80000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x80000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0xFFFF8001);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* end work arround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-}
-
-void __init
 board_io_mapping(void)
 {
 	io_block_mapping(RAINIER_IO_PAGE_INTERPOSER_PADDR,
diff -urN /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/sycamore.c linux-bluefish/arch/ppc/platforms/4xx/sycamore.c
--- /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/sycamore.c	2002-09-19 16:08:06.000000000 +1000
+++ linux-bluefish/arch/ppc/platforms/4xx/sycamore.c	2002-10-01 15:05:55.000000000 +1000
@@ -168,108 +168,6 @@
 }

 void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end work arround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-
-}
-
-void __init
 board_io_mapping(void)
 {
 	io_block_mapping(SYCAMORE_RTC_VADDR,
diff -urN /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/walnut.c linux-bluefish/arch/ppc/platforms/4xx/walnut.c
--- /home/dgibson/kernel/linuxppc-2.5/arch/ppc/platforms/4xx/walnut.c	2002-10-04 10:36:17.000000000 +1000
+++ linux-bluefish/arch/ppc/platforms/4xx/walnut.c	2002-10-04 11:30:53.000000000 +1000
@@ -128,107 +128,6 @@
 }

 void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef (CONFIG_PCI)
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end work arround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-}
-
-void __init
 board_io_mapping(void)
 {
 	io_block_mapping(WALNUT_RTC_VADDR,

--
David Gibson			| For every complex problem there is a
david@gibson.dropbear.id.au	| solution which is simple, neat and
				| wrong.
http://www.ozlabs.org/people/dgibson

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: very minor 405GP and 405GPr PCI difference

From: Todd Poynor <hidden>
Date: 2002-10-04 18:33:13

David Gibson wrote:
+	/* Now configure the PCI->PLB windows, we only use PTM1 */
+	out_le32((void *) &(pcip->ptm1ms), 0x00000000); /* first disable */
+	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* base address */
+	out_le32((void *) &(pcip->ptm1ms), 0x80000001); /* re-enable */
+	out_le32((void *) &(pcip->ptm2ms), 0x00000000); /* disable PTM2 */
+
+	/* Zero config bars */
+	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+		early_write_config_dword(hose, hose->first_busno,
+					 PCI_FUNC(hose->first_busno), bar,
+					 0x00000000);
+		early_read_config_dword(hose, hose->first_busno,
+					PCI_FUNC(hose->first_busno), bar,
+					&bar_response);
+		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
+		    hose->first_busno, PCI_SLOT(hose->first_busno),
+		    PCI_FUNC(hose->first_busno), bar, bar_response);
+	}
Only PCI_BASE_ADDRESS_1 (aka PCIL0_PTM1BAR) needs to be set since PTM2
is disabled (Ash is already doing it this way).  My reading of the
manual would indicate that the BAR ought to be set before PTM1 is
enabled, but haven't seen any problems with this.

Could enclose the early_read_config_dword() in #ifdef DEBUG.

Rainier (NP4GS3) PMM1 is setup specially in the existing code, is this
no longer needed?

This code is fragile and tends to break on certain platforms in ways
that can't be explained by the available documentation.  I can help test
the unified version on Walnut/Sycamore/Ash if needed.


--
Todd


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: very minor 405GP and 405GPr PCI difference

From: David Gibson <hidden>
Date: 2002-10-08 04:17:58

On Fri, Oct 04, 2002 at 11:33:13AM -0700, Todd Poynor wrote:
David Gibson wrote:
quoted
+	/* Now configure the PCI->PLB windows, we only use PTM1 */
+	out_le32((void *) &(pcip->ptm1ms), 0x00000000); /* first disable */
+	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* base address */
+	out_le32((void *) &(pcip->ptm1ms), 0x80000001); /* re-enable */
+	out_le32((void *) &(pcip->ptm2ms), 0x00000000); /* disable PTM2 */
+
+	/* Zero config bars */
+	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+		early_write_config_dword(hose, hose->first_busno,
+					 PCI_FUNC(hose->first_busno), bar,
+					 0x00000000);
+		early_read_config_dword(hose, hose->first_busno,
+					PCI_FUNC(hose->first_busno), bar,
+					&bar_response);
+		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is
0x%8.8x\n",
+		    hose->first_busno, PCI_SLOT(hose->first_busno),
+		    PCI_FUNC(hose->first_busno), bar, bar_response);
+	}
Only PCI_BASE_ADDRESS_1 (aka PCIL0_PTM1BAR) needs to be set since PTM2
is disabled (Ash is already doing it this way).  My reading of the
manual would indicate that the BAR ought to be set before PTM1 is
enabled, but haven't seen any problems with this.
I guess that's true.  On the other hand, I wonder if there is merit in
setting the other BAR, just so that everything is in a known state.
Could enclose the early_read_config_dword() in #ifdef DEBUG.
Yes, good idea.
Rainier (NP4GS3) PMM1 is setup specially in the existing code, is this
no longer needed?
Well, I don't know if it's necessary - it's not there, because I
didn't notice the difference in the Rainier code before.  Now that I
do look at it, I'm confused: it appears to be setting up both PMM0 and
PMM1 to map from the same PLB addresses, but the manual specifically
prohibits overlapping PMM ranges.
This code is fragile and tends to break on certain platforms in ways
that can't be explained by the available documentation.  I can help test
the unified version on Walnut/Sycamore/Ash if needed.
Do you mean the existing code, or my proposed patch (or both).  That
would be great if you could test the code on those machines -  I don't
have a Sycamore or Ash, and I'd have to drag the Walnut out again to
test on it.

--
David Gibson			| For every complex problem there is a
david@gibson.dropbear.id.au	| solution which is simple, neat and
				| wrong.
http://www.ozlabs.org/people/dgibson

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: very minor 405GP and 405GPr PCI difference

From: Todd Poynor <hidden>
Date: 2002-10-08 19:39:39

David Gibson wrote:
quoted
Rainier (NP4GS3) PMM1 is setup specially in the existing code, is this
no longer needed?

Well, I don't know if it's necessary - it's not there, because I
didn't notice the difference in the Rainier code before.  Now that I
do look at it, I'm confused: it appears to be setting up both PMM0 and
PMM1 to map from the same PLB addresses, but the manual specifically
prohibits overlapping PMM ranges.
And the code used for MontaVista's products has diverged somehow; it has
an empty bios_fixup but code in a different place that does something
different:

	/* plb address 0x8000 0000 will be set to pci address 0x8000 0000 which
	   corresponds to PCI 9030 Dev 0x10 BAR4 */
	out_le32((void*)PMM1LA,0x80000000);
	out_le32((void*)PMM1MA,0xFFFE0001);    /* PLB range is 128KB */
	out_le32((void*)PMM1PCILA,0x80000000);
	out_le32((void*)PMM1PCIHA,0x00000000);

I'll try to figure out the story on this, but everything NP4GS3-related
seems to be murky...  NP4GS3 will probably need a custom bios_fixup that
does the above (among other things), can worry about that platform later.
quoted
This code is fragile and tends to break on certain platforms in ways
that can't be explained by the available documentation.  I can help test
the unified version on Walnut/Sycamore/Ash if needed.

Do you mean the existing code, or my proposed patch (or both).  That
would be great if you could test the code on those machines -  I don't
have a Sycamore or Ash, and I'd have to drag the Walnut out again to
test on it.
Yes, I can test your proposed code on those machines.


--
Todd


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: very minor 405GP and 405GPr PCI difference

From: David Gibson <hidden>
Date: 2002-10-09 02:14:03

On Tue, Oct 08, 2002 at 12:39:39PM -0700, Todd Poynor wrote:
David Gibson wrote:
quoted
quoted
Rainier (NP4GS3) PMM1 is setup specially in the existing code, is this
no longer needed?

Well, I don't know if it's necessary - it's not there, because I
didn't notice the difference in the Rainier code before.  Now that I
do look at it, I'm confused: it appears to be setting up both PMM0 and
PMM1 to map from the same PLB addresses, but the manual specifically
prohibits overlapping PMM ranges.
And the code used for MontaVista's products has diverged somehow; it has
an empty bios_fixup but code in a different place that does something
different:

	/* plb address 0x8000 0000 will be set to pci address 0x8000 0000
	which
	   corresponds to PCI 9030 Dev 0x10 BAR4 */
	out_le32((void*)PMM1LA,0x80000000);
	out_le32((void*)PMM1MA,0xFFFE0001);    /* PLB range is 128KB */
	out_le32((void*)PMM1PCILA,0x80000000);
	out_le32((void*)PMM1PCIHA,0x00000000);
Well, it may be in a different place, but it looks like it has the
same problem.  It is still establishing a PCI window at PLB address
0x80000000, which is the same address used for the PMM0 window - or is
that also different in the MV kernel?
I'll try to figure out the story on this, but everything NP4GS3-related
seems to be murky...  NP4GS3 will probably need a custom bios_fixup that
does the above (among other things), can worry about that platform later.
I'd be trying to work out what that mapping's actually for, first.  I
still can't see how it can possibly work - if there are overlapping
PMM windows, what actually happens to accesses in that (PLB) range?
quoted
quoted
This code is fragile and tends to break on certain platforms in ways
that can't be explained by the available documentation.  I can help test
the unified version on Walnut/Sycamore/Ash if needed.

Do you mean the existing code, or my proposed patch (or both).  That
would be great if you could test the code on those machines -  I don't
have a Sycamore or Ash, and I'd have to drag the Walnut out again to
test on it.
Yes, I can test your proposed code on those machines.
--
David Gibson			| For every complex problem there is a
david@gibson.dropbear.id.au	| solution which is simple, neat and
				| wrong.
http://www.ozlabs.org/people/dgibson

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help