Dan,
try this (since the problem is the divisor register truncation):
(((((bd->bi_intfreq + 500000) / 2500000) + 1) / 2 ) & 0x3F ) << 1;
This is bad :-(
With a frequency of 46.5MHz, you get a MII clock of 2.58MHz.
Why adding 500000 (0.5MHz) to the internal clock in this computation?
We usually do that to round up (or down) to the nearest integer.
But we do NOT want to round down, or the divisor (MII_SPEED) will be too
low.
We want to round up to the nearest integer when divided by 2*2.5MHz.
--------------------------------------------
Jean-Denis Boyer, B.Eng., System Architect
Mediatrix Telecom Inc.
4229 Garlock Street
Sherbrooke (Québec)
J1L 2C8 CANADA
(819)829-8749 x241
--------------------------------------------
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Jean-Denis Boyer wrote:
With a frequency of 46.5MHz, you get a MII clock of 2.58MHz.
OK....We'll use something else, then.
Why adding 500000 (0.5MHz) to the internal clock in this computation?
We usually do that to round up (or down) to the nearest integer.
I did it to round up so the frequencies I knew about at the time would
generate the proper results. I have to admit, I never expected to
see someone run something like 46.5 MHz. I guess when we made the
change to represent the frequency in Hz instead of MHz, the arithmetic
fell apart. In the past, we couldn't represent 46.5 MHz, it would
have been 47 MHz, so the rounding would have produced a correct result.
But we do NOT want to round down, or the divisor (MII_SPEED) will be too
low.
I'm not rounding down, there are two cases where it is rounded up, but
I guess that still isn't enough.
We want to round up to the nearest integer when divided by 2*2.5MHz.
Will this work for all cases? :
((((bd->bi_intfreq + 4999999) / 2500000) / 2 ) & 0x3F ) << 1;
-- Dan
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