David Ashley wrote:
quoted
There is a bug in linux PPC, and that's what I'm trying to resolve. Here
is the last part of the printout of the execution of that program:
You must have some unique hardware :-). I've run 10,000 iterations on a 8260
and 860 with the 2.4.18-pre7 kernel, and on my 7410 PowerBook with 2.4.11
without any failures........Let us know what you fix to make it work for you.
Thanks.
-- Dan
Maybe you can point me to some discussion of how linux operates? I mean,
once the memory is mapped with the page tables, what happens once the
process does a read to a page? Does that generate a page fault? The crucial
thing is read followed by write. I suspect the problem isn't in the setting
up of the page, but in when it gets accessed and the resultant exceptions
or interrupts that produces. It seems like all discussions on this are
outdated and only apply to older kernels...
-Dave
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David Ashley wrote:
Maybe you can point me to some discussion of how linux operates? I mean,
once the memory is mapped with the page tables, what happens once the
process does a read to a page? Does that generate a page fault?
It isn't really unique to Linux. Yes, the access can generate a page
fault, which will cause a kernel exception to load the TLB. This can
generate some weird looking, early terminated bus timing, which is
perfectly within the specifications of the hardware but isn't something
the designers always consider. I've seen this quite often on the 8xx,
but fortunately have never had to attach a logic analyzer to a 60x bus.
So, I doubt it is any Linux or software problem, but more likely something
wrong with the timing on the bus that is resulting in incorrect data
returned to a memory access.
....... It seems like all discussions on this are
outdated and only apply to older kernels...
The basic concepts of how all of this works hasn't changed much. There
have been lots of detailed updates to make it more efficient or flexible.
IIRC, somewhere around the 2.4.7 timeframe was a major VM change,
we were also making changes for tracking changed attributes and Paulus
made some other instruction page invalidate enhancements. Except at
the lowest level of processor specific MMU details, all of the PowerPC
and Linux VM is the same. A bug in the lower level functions is usually
quite obvious and quickly addressed.
-- Dan
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Dan,
Could you elaborate on the problems associated w/ bus timings that
you've seen on the 8xx? We've been seeing a lot of unexplained Oops
messages (and even crashes) on one of our hardware platforms. The only
common thread seems to be dereferncing bad pointer values, but they
occur in so many different places...
I've asked our hardware guys to take a look at the settings for the UPM
we are using to control SDRAM. Do you think we are on the right track?
Can you provide any guidance?
Thanks in advance for any help you can provide! I'll buy you a beer and
some maple candy the next time I'm up your way! :-)
John
Dan Malek wrote:
David Ashley wrote:
quoted
Maybe you can point me to some discussion of how linux operates? I mean,
once the memory is mapped with the page tables, what happens once the
process does a read to a page? Does that generate a page fault?
It isn't really unique to Linux. Yes, the access can generate a page
fault, which will cause a kernel exception to load the TLB. This can
generate some weird looking, early terminated bus timing, which is
perfectly within the specifications of the hardware but isn't something
the designers always consider. I've seen this quite often on the 8xx,
but fortunately have never had to attach a logic analyzer to a 60x bus.
So, I doubt it is any Linux or software problem, but more likely something
wrong with the timing on the bus that is resulting in incorrect data
returned to a memory access.
--
John W. Linville
LVL7 Systems, Inc.
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John W. Linville wrote:
Could you elaborate on the problems associated w/ bus timings that
you've seen on the 8xx?
I don't remember the details anymore. I just remember looking at logic
analyzer traces of the system bus around MMU faults and CPM DMA and
thinking "....so that's what they mean in this timing diagram...."
As I recall, the bus lines would start to change state, but never really
start a cycle.
.... We've been seeing a lot of unexplained Oops
messages (and even crashes) on one of our hardware platforms.
This could be for many reasons.
.... The only
common thread seems to be dereferncing bad pointer values,
Well, you aren't going to crash if you don't have bad pointer values,
so that is what you are going to see :-).
I've asked our hardware guys to take a look at the settings for the UPM
we are using to control SDRAM. Do you think we are on the right track?
Can you provide any guidance?
It could be incorrect timing. That is one of the common problems. You
don't get worst case bus timing until you fire up copyback caches, enable
the MMU, and start up the CPM DMA. The core itself can't generate back to
back DRAM cycles. Marginal timing or parts are going to show up on only
some boards.
If the DRAM timing is correct, these "weird" bus cycles don't bother DRAMs.
It usually messes up other devices glued on the 8xx bus that are trying to
decode their own address space. It isn't like this isn't documented, but
it is easy to ignore or not understand until you see it in action.
Thanks in advance for any help you can provide! I'll buy you a beer and
some maple candy the next time I'm up your way! :-)
Anything associated with UPM and SDRAM is going to cost you lots more
than a beer :-).
Good Luck.
-- Dan
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