7450 L3 undocumented register

Hi !

I'm working on L3 setup/enable code for the 745x CPUs (in order to properly
configure the second CPU L3 of Apple's Dual G4s). I've studied Apple's darwin
code and it makes use of a register that isn't documented in the 7450UM rev.2
It's SPR 984, called L3PEDT.

Anybody has a clue about it ? I also noticed that their
flush/disable/invalidate/enable sequence is a bit different that what is
documented in the above manual, they additionally tweak the MSSSR0 L3TAG
bit (possibly to clear a transcient error) and they set both L3CR data only
and instruction only bits.

So anybody has a clue about what should actually be done ?

Ben.


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