Re: Support for new Dual G4 1 Gig machines?

3 messages, 3 authors, 2002-01-29 · open the first message on its own page

Re: Support for new Dual G4 1 Gig machines?

From: Holger Bettag <hidden>
Date: 2002-01-29 15:01:08

Apparently the GHz Macs use a new CPU variant, the MPC7455. It differs
very slightly from the earlier CPUs in that it has

 - a feature to lock parts of the L1 data cache (can probably be ignored)

 - some extra SPRGs (can probably be ignored)

 - 4 additional DBATs and 4 additional IBATs. I am not sure if those
   require initialization at early startup to not interfere with later
   operation.

The real difference is in fabrication; it is the first SOI part.

Some official info here (beware of line wrap):

http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC7455&nodeId=03M943030450467M986

  Holger

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Re: Support for new Dual G4 1 Gig machines?

From: Edward Swarthout <hidden>
Date: 2002-01-29 17:01:36

Holger wrote:
4 additional DBATs and 4 additional IBATs. I am not sure if those
require initialization at early startup to not interfere with later
operation.
They are not used until enabled in HID0.

See HID0[HIGH_BAT_EN] on page 49 of
  http://e-www.motorola.com/brdata/PDFDB/docs/MPC7450TS.pdf

An debug hint for early users:

The 7455 uses bit 8 for HIGH_BAT_EN.  On the 7400/7410, bit 8 is DOZE
Enable and on the 7450 it is ignored.  So, code ported from the 7400
which happens to set bit 8 will work fine on the 7450 but cause great
grief on the 7455.  Random translations whose side effects don't get
detected until much later tend to make system debug difficult...

Ed.Swarthout@Motorola.com

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Re: Support for new Dual G4 1 Gig machines?

From: benh@kernel.crashing.org
Date: 2002-01-29 19:09:40

The 7455 uses bit 8 for HIGH_BAT_EN.  On the 7400/7410, bit 8 is DOZE
Enable and on the 7450 it is ignored.  So, code ported from the 7400
which happens to set bit 8 will work fine on the 7450 but cause great
grief on the 7455.  Random translations whose side effects don't get
detected until much later tend to make system debug difficult...
If I didn't fuck it up too much, the latest kernels will not set
the DOZE bit on those CPUs if they have a proper cputable entry
(basically copy the 7450 one).

Ben.


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