Hello,
I'm using Linux for PPC in a proprietary MPC8255-based hardware as an
embedded router system. I've been trying both Denx's kernel (as of
2001-07-23) and linuxppc_2_4 (last week's version), and everything
goes smoothly (thanks to all contributing guys...).
I have some performance numbers which I'd like to share and confront,
if possible. Core clock is 132 MHZ, and bus clock 33 Mhz.
Our hardware does not have a secondary (L2) cache (and I
wonder if it should...):
- FTP transfer ratio through the router - 0.5 to 1.5 Mbytes/s;
- # of packets per second (best case): 2000
All tests were accomplished using two fast ethernet interfaces.
Best performances where obtained with data cache disabled (yes, we
had to hack linuxppc_2_4 for that...).
Does that sound ok, compared to other 8260 systems? (8255 is almost
identical to 8260)
Any numbers or other feedbacks will be highly appreciated!
Best regards,
Scop, Ricardo mailto:scop@vanet.com.br
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From: Dan Malek <hidden> Date: 2001-11-08 19:41:35
Ricardo Scop wrote:
Does that sound ok, compared to other 8260 systems?
No, not even close. Something must be wrong with your memory
interface or system. The data cache enabled should be significantly
faster, and on an 8260 you can run all three fast ethernets at full
speed. Using FTP as a benchmark isn't usually the best choice. You
should be running carefully controlled network benchmark applications.
Thanks.
-- Dan
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On Friday 09 November 2001 00:45, Dan Malek wrote:
quoted
Even without secondary (L2) cache?
Yes. Depending upon the application, using the "backside" memory
for exclusive CPM use could be helpful.
By "backside" memory you mean ... the internal data cache, perhaps?
And, how can this be done?
[sorry for the silly questions, but I'm new to both Linux and MPC8255 memory
stuff :-( ; any pointer to documentation will be very welcome, too]
Thanks again...
~ Ricardo
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From: Dan Malek <hidden> Date: 2001-11-09 16:34:00
Ricardo Scop wrote:
By "backside" memory you mean ... the internal data cache, perhaps?
No, bad use of words on my part. The 8260 has a local bus that can only
be accessed from the CPU core and CPM (it's not on the 60x bus). Maybe
the 8255 doesn't have this feature, I don't remember.
-- Dan
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From: Jerry Van Baren <hidden> Date: 2001-11-09 18:08:14
At 11:34 AM 11/9/01 -0500, Dan Malek wrote:
Ricardo Scop wrote:
quoted
By "backside" memory you mean ... the internal data cache, perhaps?
No, bad use of words on my part. The 8260 has a local bus that can only
be accessed from the CPU core and CPM (it's not on the 60x bus). Maybe
the 8255 doesn't have this feature, I don't remember.
-- Dan
The 8255 uses the 8260 "local bus" connections for the PCI bus.
gvb
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