RE: using the little endian bit 4xx mmu

I hacked it in a few hours:
in arch/ppc/kernel/head_4xx.S

in the DTLBMissHandler
START_EXCEPTION(0x1100, DTLBMiss)

check if we want to set the bit (_PAGE_ENDIAN is defined to be 0x800)

<nl>        andi.   r22, r21, _PAGE_ENDIAN  /* Perfom endian swap on this
page */
<nl>        bne     endian_tlb_load
OAOA
/*
<nl> * mapping with endian (e) storage attribute set, see ch. 3.5.3
<nl> * in the PPC405GP User's Manual.
<nl> * (this is kind of temporary, until the SCF does the swapping
<nl> * for us) --fmarti
<nl> */
endian_tlb_load:
<nl>        li      r22, 0x0c00
<nl>        andc    r21, r21, r22           /* Make sure 20, 21 are zero */
<nl>        ori     r21, r21, 0x02e0        /* TLB LO ready to go */
<nl>
<nl>        tlbsx.  r23, 0, r20
<nl>        beq     match_exists
<nl>
<nl>        /* load the next available TLB index.
<nl>         */
<nl>        lis     r22, tlb_4xx_index@h
<nl>        ori     r22, r22, tlb_4xx_index@l
<nl>        tophys(r22, r22)
<nl>        lwz     r23, 0(r22)
<nl>        addi    r23, r23, 1
<nl>        andi.   r23, r23, (PPC4XX_TLB_SIZE-1)
<nl>        stw     r23, 0(r22)
<nl>
match_exists:
<nl>        tlbwe   r21, r23, TLB_DATA              /* Load TLB LO */
<nl>
<nl>        /* Create EPN.  This is the faulting address plus a static
<nl>         * set of bits.  These are size, valid, E, U0, and ensure
<nl>         * bits 20 and 21 are zero.
<nl>         */
<nl>        li      r22, 0x00e0                     /* Set Size=4kB, V=1,
E=1 */
<nl>        rlwimi  r20, r22, 0, 20, 31
<nl>        tlbwe   r20, r23, TLB_TAG               /* Load TLB HI */
<nl>
<nl>        /* Done...restore registers and get out of here.
<nl>         */
<nl>        mfspr   r22, SPRG6
<nl>        mfspr   r21, SPRG7
<nl>        mtspr   SPRN_PID, r22
<nl>        mtcr    r21
<nl>        mfspr   r23, SPRG5
<nl>        mfspr   r22, SPRG4
<nl>        mfspr   r21, SPRG1
<nl>        mfspr   r20, SPRG0
<nl>        rfi

it could be done nicer (less code), but I needed it fast and it is only a
temporary solution for me.


-----Original Message-----
From: Troy Benjegerdes [mailto:hozer@drgw.net]
Sent: Thursday, August 23, 2001 10:53 AM
To: Ralph Blach
Cc: Linix PPC Emmbedded
Subject: Re: using the little endian bit 4xx mmu



On Thu, Aug 23, 2001 at 01:39:15PM -0400, Ralph Blach wrote:

Is there any hope of getting an ioremap little endian in the 4xx code
so the tlb would use little endian bit in the tlb?

Do you have an implementation or a patch that does this?

I think we'd be happy to look at it if someone comes up with a nice, clean
implementation.

Most of the developers seem too busy with other problems to work on
something that might take a lot of work, but only works on a small subset
of PPC chips.

--
Troy Benjegerdes | master of mispeeling | 'da hozer' |  hozer@drgw.net
-----"If this message isn't misspelled, I didn't write it" -- Me -----
"Why do musicians compose symphonies and poets write poems? They do it
because life wouldn't have any meaning for them if they didn't. That's
why I draw cartoons. It's my life." -- Charles Shulz


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"Marti, Felix" wrote:

I hacked it in a few hours:
in arch/ppc/kernel/head_4xx.S

Ugh....we have discussed this in the past.  What is the advantage
of using this feature?  All of the existing drivers and I/O macros
are designed to handle mixing of endian modes depending upon the
processor and I/O device.  All this does is complicate a standard
set of programming interfaces that everyone expects to work as they
have in the past.

The ability to set a feature flag in the PTE and transfer that to
the TLB isn't a solution to anything.  You are going to have to
rewrite all of the standard functions, macros, and device drivers
to utilize this feature, and we haven't seen any benefit to doing this.


	-- Dan

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Dan,

Because its there, and its been hacked in here and the people here have
found it VERY useful and convienent.  4xx specific or not, the people
found it extremely convienent.


Chip

Dan Malek wrote:

"Marti, Felix" wrote:

quoted

I hacked it in a few hours:
in arch/ppc/kernel/head_4xx.S

Ugh....we have discussed this in the past.  What is the advantage
of using this feature?  All of the existing drivers and I/O macros
are designed to handle mixing of endian modes depending upon the
processor and I/O device.  All this does is complicate a standard
set of programming interfaces that everyone expects to work as they
have in the past.

The ability to set a feature flag in the PTE and transfer that to
the TLB isn't a solution to anything.  You are going to have to
rewrite all of the standard functions, macros, and device drivers
to utilize this feature, and we haven't seen any benefit to doing this.

        -- Dan

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