RE: dcache BUG()

What can happen is a lwarx to an address, in some other context a
simple store to that address (no reservation broken) then a subsequent
stwcx. to the address will appear successful.  Hmmmm.....several
ways to fix it, I wonder what will work best.....

Yes, this sounds bad.  However, I wonder if it's really the cause of this
particular bug.  I cannot find any code which does a regular store to the
d_count variables.  All writes to these counters appear to use the atomic
ops.

Brian

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Brian Kuschak wrote:

....  I cannot find any code which does a regular store to the
d_count variables.  All writes to these counters appear to use the atomic
ops.

Yeah, but there are "atomic" ops/functions/macros that underneath
can do simple read/writes without using the PowerPC reservation
instructions (because they haven't been needed on other processors).


	-- Dan

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