I am working towards porting linux on sandpoint with mpc750
I face the problem of continious spurious interrupts on booting
as per the base code SIOint is cascaded to EPIC in level triggered
mode , problem vanishes when i change it to edge triggered mode
also recall written in some intel document that external interrupts from
8259 or equivalent pic's should be cascaded to APIC in edge triggered
mode only
why this requirement for cascading the interrupts from 8259 or other pic's
to APIC/EPIC
any comment on this will help me much
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Did you start with the sandpoint port that is a part of linuxppc_2_5? If not,
you should.
If so, double-check your switch settings.
Mark
--
ashish anand wrote:
I am working towards porting linux on sandpoint with mpc750
I face the problem of continious spurious interrupts on booting
as per the base code SIOint is cascaded to EPIC in level triggered
mode , problem vanishes when i change it to edge triggered mode
also recall written in some intel document that external interrupts from
8259 or equivalent pic's should be cascaded to APIC in edge triggered
mode only
why this requirement for cascading the interrupts from 8259 or other pic's
to APIC/EPIC
any comment on this will help me much
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
BTW, the linuxppc_2_5 should "just work" for the 750 if you have the switch
settings correct.
Mark
--
"Mark A. Greer" wrote:
Did you start with the sandpoint port that is a part of linuxppc_2_5? If not,
you should.
If so, double-check your switch settings.
Mark
--
ashish anand wrote:
quoted
I am working towards porting linux on sandpoint with mpc750
I face the problem of continious spurious interrupts on booting
as per the base code SIOint is cascaded to EPIC in level triggered
mode , problem vanishes when i change it to edge triggered mode
also recall written in some intel document that external interrupts from
8259 or equivalent pic's should be cascaded to APIC in edge triggered
mode only
why this requirement for cascading the interrupts from 8259 or other pic's
to APIC/EPIC
any comment on this will help me much
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/