8260 io and caches

Hi all,

I'm currently trying to get linux running on EST SBC8260 board. I had
some problems with serial ports. Initially it just sent some garbage. I
found that serial port driver doesn't initialize BRG division factor in
SCCR register even though it assumes that it should be set to 0. I
modified my bootloader to initialize it and output looks now much
better.

There still seems to be some problems with caches. Everything is just
fine with caches disabled, but if i enable caches output doesn't look
correct. Adding some flush_dcache_range() calls to uart.c seems to fix
that problem, but shouldn't rx & tx buffers be allocated from some non
cacheable region??

Thanks

Arto

--
Arto Vuori
a-mail: avuori@ssh.com
mobile:	+358 40 754 5223

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Arto Vuori wrote:

I'm currently trying to get linux running on EST SBC8260 board. I had
some problems with serial ports.

OK.....

There still seems to be some problems with caches.

What version of processor silicon do you have?


	-- Dan

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