On Sun, Mar 19, 2000 at 09:30:55AM +0100, Michel Lanners wrote:
Hi Dan,
On 18 Mar, this message from Daniel Jacobowitz echoed through cyberspace:
quoted
Well, first of all, there are two different 'current' controlfb's. One
of them is in the PPC 2.2 tree and the other in the 2.3 tree (both
bitkeeper), I believe. Did you try both of those? I'm pretty sure I
fixed this quite thoroughly in one or the other.
2.2 works well for me, but doesn't seem to work for Andrew Fyfe,
according to the comments in 2.3. 2.2 detects my 4M, 2.3 doesn't.
quoted
Actually, on closer look, I thought that the 2.3 code was correct.
Could you compare to Andrew's observations in the comment above the
code? Is he wrong? I certainly can't see how his comment would be
unless there is a memory scheme he was not detecting, and I do not
think there is.
At least his code and comments are not _entirely_ correct for my
machine. Here's what I've found so far:
- control manages mem in chunks of 2M (a pair of DIMMs), within a
region of 8M in size.
- 2M in bank 1, and 4M, are accessed at offset 0x0.
- 2M in bank 2 are accessed at offset 6M.
- the 2.3 code doesn't detect the mem at 2M in my case. It seems
writing to 0x0 garbles the memory contents at 2M: write to
2M, write to 0x0-garbling 2M, detect 0x0, detect 2M-garbled, so nothing
detected.
Aha! This signifies a much bigger problem. If the write to 0M garbles
the read from 2M, than the two are actually the same memory location!
It's my understanding that if only 2M is present it can be accessed at
0M and 2M (and possibly other offsets). Does that seem to be wrong for
you? Perhaps it can only be accessed when in a mode that requires it?
I'll speed up then ;-)
The next step is to compile a better detection check, that can detect
mirrored memory regions, so that I can find out what's wrong between
0x0 and 2M..... It's actually very strange, as my 4M do work when
accessed in one block starting at 0x0... so 2M would have to be
different from 0x0 ???
Try running the check after switching to a vmode which requires more
than 2M, please.
By the way, somewhere I have an alternate OF driver for control, that
IIRC came out of darwin, and it ver accesses VRAM only at 0x0 or 6M....
Unfortunately, it's too big to fit into nvramrc ;-))
Hmmm.......
Dan
/--------------------------------\ /--------------------------------\
| Daniel Jacobowitz |__| SCS Class of 2002 |
| Debian GNU/Linux Developer __ Carnegie Mellon University |
| dan@debian.org | | dmj+@andrew.cmu.edu |
\--------------------------------/ \--------------------------------/
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
Hi list,
Here's another test patch for the detection problem on controlfb.
Again, this doesn't fix any problem, it's just to get a better
understanding of what happens in control..
I've also set up a little web page about the issue:
http://piglet.grunz.lu/~mlan/linux/dev/control.html
Please boot a kernel with this patch included ASAP and report your
results back to me! Thanks.
For the interested, there's more below...
On 19 Mar, this message from Daniel Jacobowitz echoed through cyberspace:
quoted
Here's what I've found so far:
- control manages mem in chunks of 2M (a pair of DIMMs), within a
region of 8M in size.
- 2M in bank 1, and 4M, are accessed at offset 0x0.
- 2M in bank 2 are accessed at offset 6M.
- the 2.3 code doesn't detect the mem at 2M in my case. It seems
writing to 0x0 garbles the memory contents at 2M: write to
2M, write to 0x0-garbling 2M, detect 0x0, detect 2M-garbled, so nothing
detected.
Aha! This signifies a much bigger problem. If the write to 0M garbles
the read from 2M, than the two are actually the same memory location!
It's my understanding that if only 2M is present it can be accessed at
0M and 2M (and possibly other offsets). Does that seem to be wrong for
you? Perhaps it can only be accessed when in a mode that requires it?
The detection code seems to indicate garbling; however, practical
experience seems to contradict that:
quoted
The next step is to compile a better detection check, that can detect
mirrored memory regions, so that I can find out what's wrong between
0x0 and 2M..... It's actually very strange, as my 4M do work when
accessed in one block starting at 0x0... so 2M would have to be
different from 0x0 ???
Try running the check after switching to a vmode which requires more
than 2M, please.
That's precisely what I run: 1152x870 at 32 bpp. Except when controlfb
only detects 2MB and sets me back to 16 bpp...
So, yes, under 2.2 kernels, I do use all my 4MB of VRAM, and they are
accessed as a single block starting at 0x0! Which indicates the mem at
2MB is _not_ the same as at 0x0.....
Anyway, below is yet another test patch which also checks for mirrored
locations. Have fun!
-------------------------------------------------------------------------
Michel Lanners | " Read Philosophy. Study Art.
23, Rue Paul Henkes | Ask Questions. Make Mistakes.
L-1710 Luxembourg |
email mlan@cpu.lu |
http://www.cpu.lu/~mlan | Learn Always. "
Stupidity struck...
On 19 Mar, this message from <stupid> was heard:
I've also set up a little web page about the issue:
Ooopss... that was my home machine, as seen in my internal DNS.
Here's the right URL:
http://www.cpu.lu/~mlan/linux/dev/control.html
Have fun, and test lots!
Michel
-------------------------------------------------------------------------
Michel Lanners | " Read Philosophy. Study Art.
23, Rue Paul Henkes | Ask Questions. Make Mistakes.
L-1710 Luxembourg |
email mlan@cpu.lu |
http://www.cpu.lu/~mlan | Learn Always. "
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
At 1:24 PM -0500 3/19/00, Michel Lanners wrote:
Stupidity struck...
On 19 Mar, this message from <stupid> was heard:
quoted
I've also set up a little web page about the issue:
Ooopss... that was my home machine, as seen in my internal DNS.
Here's the right URL:
http://www.cpu.lu/~mlan/linux/dev/control.html
The phenomenon you're describing is called aliasing. It happens all over
the place on 68k Macs.
To check for this you divide the RAM into blocks that you think are aliased
(like 1Meg blocks in the case of the Control VRAM). Usually, blocks in low
memory are aliased into high memory. So what you do is write a unique value
into each block from high memory to low memory. Then you go back and read
the values and the answers become obvious:
So if you write 4 3 2 1 into each block and get back 2 1 2 1 then it is
easy to see that banks 4 and 3 are aliases of banks 2 and 1 respectively.
This can be done with a couple of for loops which should tighten up your
code a little.
You may also wish to reverse engineer some of the ROM routines or the Apple
drivers. These usually contain code which sizes the VRAM. Rather than
probing for RAM like, this you might be able to just read a few bits out of
a memory controller chip somewhere. At least on the Quadras the memory
controller was capable of telling you what kind of VRAM was in use but you
had to size it by hand using the technique above.
Good luck!
____________________________________________________________________
Michael Zucca - mrz5149@acm.org - http://www.mdc.net/~mrz5149/
"I will choose a path that's clear. I will choose Freewill. "
--Rush, Freewill
____________________________________________________________________
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