Re: FireWire + Apple PB G3: some success

From: Albrecht Dreß <redacted>
Subject: Re: FireWire + Apple PB G3: some success
Date: Mon, 28 Feb 2000 13:59:14 +0100
Message-ID: [off-list ref]

01:00.0 FireWire (IEEE 1394): Texas Instruments PCILynx/PCILynx2 IEEE 1394 Link
Layer Controller (rev 04) (prog-if 00 [Generic])
        Subsystem: Texas Instruments: Unknown device 8000
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 1 min, 2 max, 32 set, cache line size 20
        Interrupt: pin A routed to IRQ 0

                                     ^^^^^^

        Region 0: Memory at 90030000 (32-bit, non-prefetchable)
        Region 1: Memory at 90000000 (32-bit, non-prefetchable)
        Region 2: Memory at 90010000 (32-bit, non-prefetchable)
        Expansion ROM at 90020000

I think IRQ 0 is a little bit suspicious, right?  At least /proc/interrupts does
not count ANY irq's on this line.  The same information for the Cardbus bridge
is-

00:13.0 CardBus bridge: Texas Instruments: Unknown device ac1e

                                                            ^^^^

        Subsystem: Texas Instruments: Unknown device ac1e
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
        Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
        Latency: 32 set, cache line size 08
        Interrupt: pin A routed to IRQ 22
        Region 0: Memory at 80880000 (32-bit, non-prefetchable)
        Bus: primary=00, secondary=01, subordinate=04, sec-latency=64
Memory window 0: 90000000-90031000
        I/O window 0: 00000000-00000003
        I/O window 1: 00000000-00000003
        BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt+ PostWrite+
        16-bit legacy interface ports at 0007

Have you checked if the patch you used is really working correctly?
It setups CardBus bridge's interrupt routing for only TI1130(0xac12)
and TI1131(0xac15) (see the patch to arch/ppc/kernel/pmac_pci.c).
You will have to add support for your CardBus bridge(ID 0xac1e)
referring the document from TI.

Regards,


Ryuichi Oikawa
roikawa@rr.iij4u.or.jp

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On Wed, Mar 1, 2000, Ryuichi Oikawa [off-list ref] wrote:

Have you checked if the patch you used is really working correctly?
It setups CardBus bridge's interrupt routing for only TI1130(0xac12)
and TI1131(0xac15) (see the patch to arch/ppc/kernel/pmac_pci.c).
You will have to add support for your CardBus bridge(ID 0xac1e)
referring the document from TI.

ac1e is the TI-1211. This is the same CardBus chip used in the new Pismo
powerbook. It's datasheet can be found on TI web site with the complete
register set.

BTW. I didn't find register infos in the datasheet for the TI-1131. Do
you have those ? I'd be interested. I found only the pinout and
electrical specs.


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Ryuichi Oikawa wrote:

Have you checked if the patch you used is really working correctly?
It setups CardBus bridge's interrupt routing for only TI1130(0xac12)
and TI1131(0xac15) (see the patch to arch/ppc/kernel/pmac_pci.c).
You will have to add support for your CardBus bridge(ID 0xac1e)
referring the document from TI.

I also found that problem as I could not see the pcibios_fixup kernel message in
the logs...

As Ben already said, it it TI's PCI1211.  Although the data sheet states that
the two registers you alter with your patch (0x91 and 0x91) are "...provided for
PCI1130 campatibility", just adding the signature to activate the setup does not
work.

Unfortunately I do not have a card for which I know for sure that it will work
with LinuxPPC.  In the meantime I tested so many different combinations of
with/without your patch, with/without the PCMCIA package ver. 3.0.something/
3.1.something enables/diabled and an Adaptec SCSI CardBus Card/FireWire2Go
CardBus card (and got all sorts of nasty reactions like freezes and panics) that
I am a litte confused now.  I am afraid I have to try a more systematic
approach, and to read TI's docs first.

Anyway, thanks a lot for your help!

Yours, Albrecht.


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