On Tue, 10 Jun 2025 17:41:36 +0900
Masami Hiramatsu (Google) [off-list ref] wrote:

SERIALIZE instruction may flash pipeline, thus the processor needs
to reload the instruction. But it is not ensured to reload it from
memory because SERIALIZE does not invalidate the cache.

From my understanding, an IPI on a CPU is equivalent to a smp_mb() on that
CPU. There shouldn't be any need for flushing the cache.

If that hypotheses is correct, we need to invalidate the cache
(flush TLB) in the third step, before the do_sync_core().

I'm not sure how the TLB would be affected.

-- Steve

Or, if it is unsure, we can just evacuate the kernel from die("int3")
by retrying the new instruction, when the INT3 is disappeared.