[PATCH v2 resend] serial: 8250_dw: fix wrong logic in dw8250_check_lcr()
From: Kefeng Wang <hidden>
Date: 2016-04-05 02:52:44
Also in:
lkml
Subsystem:
8250/16?50 (and clone uarts) serial driver, synopsys designware 8250 uart driver, the rest, tty layer and serial drivers · Maintainers:
Greg Kroah-Hartman, Ilpo Järvinen, Linus Torvalds, Jiri Slaby
Commit cdcea058e510 ("serial: 8250_dw: Avoid serial_outx code duplicate
with new dw8250_check_lcr()") introduce a wrong logic when write val to
LCR reg. When CONFIG_64BIT enabled, __raw_writeq is used unconditionally.
The __raw_readq/__raw_writeq is introduced by commit bca2092d7897 ("serial:
8250_dw: Use 64-bit access for OCTEON.") for OCTEON, so for !PORT_OCTEON,
we better to use coincident write func.
Fixes: cdcea058e510("serial: 8250_dw: Avoid serial_outx code duplicate with new dw8250_check_lcr()")
Signed-off-by: Kefeng Wang <redacted>
---
drivers/tty/serial/8250/8250_dw.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index a3fb95d..003ce60 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c@@ -103,16 +103,14 @@ static void dw8250_check_lcr(struct uart_port *p, int value) dw8250_force_idle(p); -#ifdef CONFIG_64BIT - __raw_writeq(value & 0xff, offset); -#else - if (p->iotype == UPIO_MEM32) + if (IS_ENABLED(CONFIG_64BIT) && p->type == PORT_OCTEON) + __raw_writeq(value & 0xff, offset); + else if (p->iotype == UPIO_MEM32) writel(value, offset); else if (p->iotype == UPIO_MEM32BE) iowrite32be(value, offset); else writeb(value, offset); -#endif } /* * FIXME: this deadlocks if port->lock is already held
--
2.6.0.GIT