--- v6
+++ v3
@@ -12,27 +12,23 @@
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
-Signed-off-by: Horia Geanta <horia.geanta@nxp.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766 +++++++++++++++++++++++++
- 1 file changed, 766 insertions(+)
+ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 693 +++++++++++++++++++++++++
+ 1 file changed, 693 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
new file mode 100644
-index 0000000..9fcfd48
+index 0000000..46eea16
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
-@@ -0,0 +1,766 @@
+@@ -0,0 +1,693 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A family SoC.
+//
+// Copyright 2018 NXP
+
-+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
@@ -51,7 +47,6 @@
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ d-cache-size = <0x8000>;
@@ -66,7 +61,6 @@
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x1>;
+ clocks = <&clockgen 1 0>;
+ d-cache-size = <0x8000>;
@@ -81,7 +75,6 @@
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x100>;
+ clocks = <&clockgen 1 1>;
+ d-cache-size = <0x8000>;
@@ -96,7 +89,6 @@
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x101>;
+ clocks = <&clockgen 1 1>;
+ d-cache-size = <0x8000>;
@@ -111,7 +103,6 @@
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x200>;
+ clocks = <&clockgen 1 2>;
+ d-cache-size = <0x8000>;
@@ -126,7 +117,6 @@
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x201>;
+ clocks = <&clockgen 1 2>;
+ d-cache-size = <0x8000>;
@@ -141,7 +131,6 @@
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x300>;
+ clocks = <&clockgen 1 3>;
+ d-cache-size = <0x8000>;
@@ -156,7 +145,6 @@
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x301>;
+ clocks = <&clockgen 1 3>;
+ d-cache-size = <0x8000>;
@@ -171,7 +159,6 @@
+ cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x400>;
+ clocks = <&clockgen 1 4>;
+ d-cache-size = <0x8000>;
@@ -186,7 +173,6 @@
+ cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x401>;
+ clocks = <&clockgen 1 4>;
+ d-cache-size = <0x8000>;
@@ -201,7 +187,6 @@
+ cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x500>;
+ clocks = <&clockgen 1 5>;
+ d-cache-size = <0x8000>;
@@ -216,7 +201,6 @@
+ cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x501>;
+ clocks = <&clockgen 1 5>;
+ d-cache-size = <0x8000>;
@@ -231,7 +215,6 @@
+ cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x600>;
+ clocks = <&clockgen 1 6>;
+ d-cache-size = <0x8000>;
@@ -246,7 +229,6 @@
+ cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x601>;
+ clocks = <&clockgen 1 6>;
+ d-cache-size = <0x8000>;
@@ -261,7 +243,6 @@
+ cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x700>;
+ clocks = <&clockgen 1 7>;
+ d-cache-size = <0x8000>;
@@ -276,7 +257,6 @@
+ cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
-+ enable-method = "psci";
+ reg = <0x701>;
+ clocks = <&clockgen 1 7>;
+ d-cache-size = <0x8000>;
@@ -366,7 +346,7 @@
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
-+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <1 9 0x4>;
+
+ its: gic-its@6020000 {
+ compatible = "arm,gic-v3-its";
@@ -375,17 +355,22 @@
+ };
+ };
+
++ rstcr: syscon@1e60000 {
++ compatible = "syscon";
++ reg = <0x0 0x1e60000 0x0 0x4>;
++ };
++
+ timer {
+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <1 13 4>,
++ <1 14 4>,
++ <1 11 4>,
++ <1 10 4>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
-+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
++ interrupts = <1 7 0x8>; // PMU PPI, Level low type
+ };
+
+ psci {
@@ -402,18 +387,17 @@
+ ddr1: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 17 0x4>;
+ little-endian;
+ };
+
+ ddr2: memory-controller@1090000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1090000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 18 0x4>;
+ little-endian;
+ };
+
-+ // One clock unit-sysclk node which bootloader require during DT fix-up
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
@@ -426,6 +410,13 @@
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
++
++ clockgen: clocking@1300000 {
++ compatible = "fsl,lx2160a-clockgen";
++ reg = <0 0x1300000 0 0xa0000>;
++ #clock-cells = <2>;
++ clocks = <&sysclk>;
++ };
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
@@ -467,170 +458,16 @@
+ };
+ };
+
-+ clockgen: clock-controller@1300000 {
-+ compatible = "fsl,lx2160a-clockgen";
-+ reg = <0 0x1300000 0 0xa0000>;
-+ #clock-cells = <2>;
-+ clocks = <&sysclk>;
-+ };
-+
-+ dcfg: syscon@1e00000 {
++ dcfg: dcfg@1e00000 {
+ compatible = "fsl,lx2160a-dcfg", "syscon";
+ reg = <0x0 0x1e00000 0x0 0x10000>;
+ little-endian;
+ };
+
-+ i2c0: i2c@2000000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2000000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ i2c1: i2c@2010000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2010000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c2: i2c@2020000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2020000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c3: i2c@2030000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2030000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c4: i2c@2040000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2040000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
-+ status = "disabled";
-+ };
-+
-+ i2c5: i2c@2050000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2050000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c6: i2c@2060000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2060000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ i2c7: i2c@2070000 {
-+ compatible = "fsl,vf610-i2c";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0 0x2070000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-names = "i2c";
-+ clocks = <&clockgen 4 7>;
-+ status = "disabled";
-+ };
-+
-+ esdhc0: esdhc@2140000 {
-+ compatible = "fsl,esdhc";
-+ reg = <0x0 0x2140000 0x0 0x10000>;
-+ interrupts = <0 28 0x4>; /* Level high type */
-+ clocks = <&clockgen 4 1>;
-+ voltage-ranges = <1800 1800 3300 3300>;
-+ sdhci,auto-cmd12;
-+ little-endian;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ esdhc1: esdhc@2150000 {
-+ compatible = "fsl,esdhc";
-+ reg = <0x0 0x2150000 0x0 0x10000>;
-+ interrupts = <0 63 0x4>; /* Level high type */
-+ clocks = <&clockgen 4 1>;
-+ voltage-ranges = <1800 1800 3300 3300>;
-+ sdhci,auto-cmd12;
-+ broken-cd;
-+ little-endian;
-+ bus-width = <4>;
-+ status = "disabled";
-+ };
-+
-+ uart0: serial@21c0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21c0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@21d0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21d0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ uart2: serial@21e0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21e0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
-+ uart3: serial@21f0000 {
-+ compatible = "arm,sbsa-uart","arm,pl011";
-+ reg = <0x0 0x21f0000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-+ current-speed = <115200>;
-+ status = "disabled";
-+ };
-+
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 36 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
@@ -641,7 +478,7 @@
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 36 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
@@ -652,7 +489,7 @@
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 37 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
@@ -663,7 +500,7 @@
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 37 0x4>; // Level high type
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
@@ -671,31 +508,130 @@
+ #interrupt-cells = <2>;
+ };
+
-+ watchdog@23a0000 {
-+ compatible = "arm,sbsa-gwdt";
-+ reg = <0x0 0x23a0000 0 0x1000>,
-+ <0x0 0x2390000 0 0x1000>;
-+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-+ timeout-sec = <30>;
-+ };
-+
-+ usb0: usb@3100000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3100000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
-+ status = "disabled";
-+ };
-+
-+ usb1: usb@3110000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x3110000 0x0 0x10000>;
-+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-+ dr_mode = "host";
-+ snps,quirk-frame-length-adjustment = <0x20>;
-+ snps,dis_rxdet_inp3_quirk;
++
++ i2c0: i2c@2000000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2000000 0x0 0x10000>;
++ interrupts = <0 34 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ fsl-scl-gpio = <&gpio2 15 0>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@2010000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2010000 0x0 0x10000>;
++ interrupts = <0 34 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@2020000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2020000 0x0 0x10000>;
++ interrupts = <0 35 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@2030000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2030000 0x0 0x10000>;
++ interrupts = <0 35 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ status = "disabled";
++ };
++
++ i2c4: i2c@2040000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2040000 0x0 0x10000>;
++ interrupts = <0 74 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ fsl-scl-gpio = <&gpio2 16 0>;
++ status = "disabled";
++ };
++
++ i2c5: i2c@2050000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2050000 0x0 0x10000>;
++ interrupts = <0 74 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ status = "disabled";
++ };
++
++ i2c6: i2c@2060000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2060000 0x0 0x10000>;
++ interrupts = <0 75 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ status = "disabled";
++ };
++
++ i2c7: i2c@2070000 {
++ compatible = "fsl,vf610-i2c";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0 0x2070000 0x0 0x10000>;
++ interrupts = <0 75 0x4>; // Level high type
++ clock-names = "i2c";
++ clocks = <&clockgen 4 7>;
++ status = "disabled";
++ };
++
++ uart0: serial@21c0000 {
++ device_type = "serial";
++ compatible = "arm,pl011","arm,sbsa-uart";
++ reg = <0x0 0x21c0000 0x0 0x1000>;
++ interrupts = <0 32 0x4>; // Level high type
++ current-speed = <115200>;
++ status = "disabled";
++ };
++
++ uart1: serial@21d0000 {
++ device_type = "serial";
++ compatible = "arm,pl011","arm,sbsa-uart";
++ reg = <0x0 0x21d0000 0x0 0x1000>;
++ interrupts = <0 33 0x4>; // Level high type
++ current-speed = <115200>;
++ status = "disabled";
++ };
++
++ uart2: serial@21e0000 {
++ device_type = "serial";
++ compatible = "arm,pl011","arm,sbsa-uart";
++ reg = <0x0 0x21e0000 0x0 0x1000>;
++ interrupts = <0 72 0x4>; // Level high type
++ current-speed = <115200>;
++ status = "disabled";
++ };
++
++ uart3: serial@21f0000 {
++ device_type = "serial";
++ compatible = "arm,pl011","arm,sbsa-uart";
++ reg = <0x0 0x21f0000 0x0 0x1000>;
++ interrupts = <0 73 0x4>; // Level high type
++ current-speed = <115200>;
+ status = "disabled";
+ };
+
@@ -704,92 +640,80 @@
+ reg = <0 0x5000000 0 0x800000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <14>;
-+ // global secure fault
-+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-+ // combined secure
-+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-+ // global non-secure fault
-+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-+ // combined non-secure
-+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-+ // performance counter interrupts 0-9
-+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
-+ // per context interrupt, 64 interrupts
-+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <0 13 4>, // global secure fault
++ <0 14 4>, // combined secure interrupt
++ <0 15 4>, // global non-secure fault
++ <0 16 4>, // combined non-secure interrupt
++ // performance counter interrupts 0-9
++ <0 211 4>, <0 212 4>,
++ <0 213 4>, <0 214 4>,
++ <0 215 4>, <0 216 4>,
++ <0 217 4>, <0 218 4>,
++ <0 219 4>, <0 220 4>,
++ // per context interrupt, 64 interrupts
++ <0 146 4>, <0 147 4>,
++ <0 148 4>, <0 149 4>,
++ <0 150 4>, <0 151 4>,
++ <0 152 4>, <0 153 4>,
++ <0 154 4>, <0 155 4>,
++ <0 156 4>, <0 157 4>,
++ <0 158 4>, <0 159 4>,
++ <0 160 4>, <0 161 4>,
++ <0 162 4>, <0 163 4>,
++ <0 164 4>, <0 165 4>,
++ <0 166 4>, <0 167 4>,
++ <0 168 4>, <0 169 4>,
++ <0 170 4>, <0 171 4>,
++ <0 172 4>, <0 173 4>,
++ <0 174 4>, <0 175 4>,
++ <0 176 4>, <0 177 4>,
++ <0 178 4>, <0 179 4>,
++ <0 180 4>, <0 181 4>,
++ <0 182 4>, <0 183 4>,
++ <0 184 4>, <0 185 4>,
++ <0 186 4>, <0 187 4>,
++ <0 188 4>, <0 189 4>,
++ <0 190 4>, <0 191 4>,
++ <0 192 4>, <0 193 4>,
++ <0 194 4>, <0 195 4>,
++ <0 196 4>, <0 197 4>,
++ <0 198 4>, <0 199 4>,
++ <0 200 4>, <0 201 4>,
++ <0 202 4>, <0 203 4>,
++ <0 204 4>, <0 205 4>,
++ <0 206 4>, <0 207 4>,
++ <0 208 4>, <0 209 4>;
+ dma-coherent;
+ };
++
++ usb0: usb3@3100000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0x3100000 0x0 0x10000>;
++ interrupts = <0 80 0x4>; // Level high type
++ dr_mode = "host";
++ snps,quirk-frame-length-adjustment = <0x20>;
++ snps,dis_rxdet_inp3_quirk;
++ status = "disabled";
++ };
++
++ usb1: usb3@3110000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0x3110000 0x0 0x10000>;
++ interrupts = <0 81 0x4>; // Level high type
++ dr_mode = "host";
++ snps,quirk-frame-length-adjustment = <0x20>;
++ snps,dis_rxdet_inp3_quirk;
++ status = "disabled";
++ };
++
++ watchdog@23a0000 {
++ compatible = "arm,sbsa-gwdt";
++ reg = <0x0 0x23a0000 0 0x1000>,
++ <0x0 0x2390000 0 0x1000>;
++ interrupts = <0 59 4>;
++ timeout-sec = <30>;
++ };
++
+ };
+};
--